prev_cmp_ram.qmsg

nios 中读写sdram的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 23 14:02:23 2008 " "Info: Processing started: Sat Aug 23 14:02:23 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ram -c ram " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ram -c ram" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "142 " "Info: Allocated 142 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 23 14:02:27 2008 " "Info: Processing ended: Sat Aug 23 14:02:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 23 14:02:28 2008 " "Info: Processing started: Sat Aug 23 14:02:28 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off ram -c ram --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ram -c ram --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock memory memory lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\] 163.03 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 163.03 MHz between source memory \"lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg\" and destination memory \"lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.639 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg 1 MEM M4K_X27_Y7 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.639 ns) 3.639 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\] 2 MEM M4K_X27_Y7 1 " "Info: 2: + IC(0.000 ns) + CELL(3.639 ns) = 3.639 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 33 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.639 ns ( 100.00 % ) " "Info: Total cell delay = 3.639 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.639 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns } { 0.000ns 3.639ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.057 ns - Smallest " "Info: - Smallest clock skew is -0.057 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.931 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 2.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clock~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(0.821 ns) 2.931 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\] 3 MEM M4K_X27_Y7 1 " "Info: 3: + IC(0.831 ns) + CELL(0.821 ns) = 2.931 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.652 ns" { clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 33 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.961 ns ( 66.91 % ) " "Info: Total cell delay = 1.961 ns ( 66.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 33.09 % ) " "Info: Total interconnect delay = 0.970 ns ( 33.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.931 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.9