prev_cmp_ram.tan.qmsg

nios 中读写sdram的程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock memory memory lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\] 163.03 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 163.03 MHz between source memory \"lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg\" and destination memory \"lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.639 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg 1 MEM M4K_X27_Y7 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.639 ns) 3.639 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\] 2 MEM M4K_X27_Y7 1 " "Info: 2: + IC(0.000 ns) + CELL(3.639 ns) = 3.639 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 33 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.639 ns ( 100.00 % ) " "Info: Total cell delay = 3.639 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.639 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns } { 0.000ns 3.639ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.057 ns - Smallest " "Info: - Smallest clock skew is -0.057 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.931 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 2.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clock~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(0.821 ns) 2.931 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\] 3 MEM M4K_X27_Y7 1 " "Info: 3: + IC(0.831 ns) + CELL(0.821 ns) = 2.931 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.652 ns" { clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 33 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.961 ns ( 66.91 % ) " "Info: Total cell delay = 1.961 ns ( 66.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 33.09 % ) " "Info: Total interconnect delay = 0.970 ns ( 33.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.931 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.931 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.821ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.988 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.988 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clock~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(0.878 ns) 2.988 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg 3 MEM M4K_X27_Y7 8 " "Info: 3: + IC(0.831 ns) + CELL(0.878 ns) = 2.988 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.018 ns ( 67.54 % ) " "Info: Total cell delay = 2.018 ns ( 67.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 32.46 % ) " "Info: Total interconnect delay = 0.970 ns ( 32.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.988 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.988 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.931 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.931 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.821ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.988 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.988 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 38 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 33 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.639 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.639 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns } { 0.000ns 3.639ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.931 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.931 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.821ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.988 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.988 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] {} } { 0.000ns } { 0.109ns } "" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 33 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg rden clock 5.568 ns memory " "Info: tsu for memory \"lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg\" (data pin = \"rden\", clock pin = \"clock\") is 5.568 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.510 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.510 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns rden 1 PIN PIN_142 1 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_142; Fanout = 1; PIN Node = 'rden'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rden } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 312 496 664 328 "rden" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.137 ns) + CELL(0.388 ns) 8.510 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg 2 MEM M4K_X27_Y7 8 " "Info: 2: + IC(7.137 ns) + CELL(0.388 ns) = 8.510 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.525 ns" { rden lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns ( 16.13 % ) " "Info: Total cell delay = 1.373 ns ( 16.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.137 ns ( 83.87 % ) " "Info: Total interconnect delay = 7.137 ns ( 83.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.510 ns" { rden lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.510 ns" { rden {} rden~combout {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg {} } { 0.000ns 0.000ns 7.137ns } { 0.000ns 0.985ns 0.388ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 38 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.988 ns - Shortest memory " "Info: - Shortest clock path from clock \"clock\" to destination memory is 2.988 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clock~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(0.878 ns) 2.988 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg 3 MEM M4K_X27_Y7 8 " "Info: 3: + IC(0.831 ns) + CELL(0.878 ns) = 2.988 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_re_reg'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.018 ns ( 67.54 % ) " "Info: Total cell delay = 2.018 ns ( 67.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 32.46 % ) " "Info: Total interconnect delay = 0.970 ns ( 32.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.988 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.988 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.510 ns" { rden lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.510 ns" { rden {} rden~combout {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg {} } { 0.000ns 0.000ns 7.137ns } { 0.000ns 0.985ns 0.388ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.988 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.988 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[7\] lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[7\] 9.930 ns memory " "Info: tco from clock \"clock\" to destination pin \"q\[7\]\" through memory \"lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[7\]\" is 9.930 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.931 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to source memory is 2.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clock~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(0.821 ns) 2.931 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[7\] 3 MEM M4K_X27_Y7 1 " "Info: 3: + IC(0.831 ns) + CELL(0.821 ns) = 2.931 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.652 ns" { clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 33 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.961 ns ( 66.91 % ) " "Info: Total cell delay = 1.961 ns ( 66.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 33.09 % ) " "Info: Total interconnect delay = 0.970 ns ( 33.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.931 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.931 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.821ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 33 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.739 ns + Longest memory pin " "Info: + Longest memory to pin delay is 6.739 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[7\] 1 MEM M4K_X27_Y7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|q_b\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 33 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.534 ns) + CELL(3.096 ns) 6.739 ns q\[7\] 2 PIN PIN_30 0 " "Info: 2: + IC(3.534 ns) + CELL(3.096 ns) = 6.739 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'q\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.630 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] q[7] } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 296 1048 1224 312 "q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.205 ns ( 47.56 % ) " "Info: Total cell delay = 3.205 ns ( 47.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.534 ns ( 52.44 % ) " "Info: Total interconnect delay = 3.534 ns ( 52.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.739 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] q[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.739 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] {} q[7] {} } { 0.000ns 3.534ns } { 0.109ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.931 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.931 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.821ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.739 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] q[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.739 ns" { lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] {} q[7] {} } { 0.000ns 3.534ns } { 0.109ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_address_reg3 rdaddress\[3\] clock 0.286 ns memory " "Info: th for memory \"lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_address_reg3\" (data pin = \"rdaddress\[3\]\", clock pin = \"clock\") is 0.286 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.988 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to destination memory is 2.988 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clock 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clock~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 336 496 664 352 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(0.878 ns) 2.988 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_address_reg3 3 MEM M4K_X27_Y7 8 " "Info: 3: + IC(0.831 ns) + CELL(0.878 ns) = 2.988 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_address_reg3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.018 ns ( 67.54 % ) " "Info: Total cell delay = 2.018 ns ( 67.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 32.46 % ) " "Info: Total interconnect delay = 0.970 ns ( 32.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.988 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.988 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3 {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.267 ns + " "Info: + Micro hold delay of destination is 0.267 ns" {  } { { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 38 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.969 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 2.969 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns rdaddress\[3\] 1 PIN PIN_131 1 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_131; Fanout = 1; PIN Node = 'rdaddress\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdaddress[3] } "NODE_NAME" } } { "ram.bdf" "" { Schematic "E:/ram/ram.bdf" { { 296 496 664 312 "rdaddress\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.643 ns) + CELL(0.176 ns) 2.969 ns lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_address_reg3 2 MEM M4K_X27_Y7 8 " "Info: 2: + IC(1.643 ns) + CELL(0.176 ns) = 2.969 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst\|altsyncram:altsyncram_component\|altsyncram_47r1:auto_generated\|ram_block1a0~portb_address_reg3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.819 ns" { rdaddress[3] lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "db/altsyncram_47r1.tdf" "" { Text "E:/ram/db/altsyncram_47r1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.326 ns ( 44.66 % ) " "Info: Total cell delay = 1.326 ns ( 44.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.643 ns ( 55.34 % ) " "Info: Total interconnect delay = 1.643 ns ( 55.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.969 ns" { rdaddress[3] lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.969 ns" { rdaddress[3] {} rdaddress[3]~combout {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3 {} } { 0.000ns 0.000ns 1.643ns } { 0.000ns 1.150ns 0.176ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.988 ns" { clock clock~clkctrl lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.988 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3 {} } { 0.000ns 0.000ns 0.139ns 0.831ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.969 ns" { rdaddress[3] lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.969 ns" { rdaddress[3] {} rdaddress[3]~combout {} lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3 {} } { 0.000ns 0.000ns 1.643ns } { 0.000ns 1.150ns 0.176ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}