ram.tan.rpt

nios 中读写sdram的程序

    Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 3.639 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg'
            Info: 2: + IC(0.000 ns) + CELL(3.639 ns) = 3.639 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0]'
            Info: Total cell delay = 3.639 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.057 ns
            Info: + Shortest clock path from clock "clock" to destination memory is 2.931 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.831 ns) + CELL(0.821 ns) = 2.931 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0]'
                Info: Total cell delay = 1.961 ns ( 66.91 % )
                Info: Total interconnect delay = 0.970 ns ( 33.09 % )
            Info: - Longest clock path from clock "clock" to source memory is 2.988 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.831 ns) + CELL(0.878 ns) = 2.988 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg'
                Info: Total cell delay = 2.018 ns ( 67.54 % )
                Info: Total interconnect delay = 0.970 ns ( 32.46 % )
        Info: + Micro clock to output delay of source is 0.260 ns
        Info: + Micro setup delay of destination is 0.046 ns
Info: tsu for memory "lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg" (data pin = "rden", clock pin = "clock") is 5.568 ns
    Info: + Longest pin to memory delay is 8.510 ns
        Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_142; Fanout = 1; PIN Node = 'rden'
        Info: 2: + IC(7.137 ns) + CELL(0.388 ns) = 8.510 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg'
        Info: Total cell delay = 1.373 ns ( 16.13 % )
        Info: Total interconnect delay = 7.137 ns ( 83.87 % )
    Info: + Micro setup delay of destination is 0.046 ns
    Info: - Shortest clock path from clock "clock" to destination memory is 2.988 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.831 ns) + CELL(0.878 ns) = 2.988 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_re_reg'
        Info: Total cell delay = 2.018 ns ( 67.54 % )
        Info: Total interconnect delay = 0.970 ns ( 32.46 % )
Info: tco from clock "clock" to destination pin "q[7]" through memory "lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7]" is 9.930 ns
    Info: + Longest clock path from clock "clock" to source memory is 2.931 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.831 ns) + CELL(0.821 ns) = 2.931 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7]'
        Info: Total cell delay = 1.961 ns ( 66.91 % )
        Info: Total interconnect delay = 0.970 ns ( 33.09 % )
    Info: + Micro clock to output delay of source is 0.260 ns
    Info: + Longest memory to pin delay is 6.739 ns
        Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X27_Y7; Fanout = 1; MEM Node = 'lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7]'
        Info: 2: + IC(3.534 ns) + CELL(3.096 ns) = 6.739 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'q[7]'
        Info: Total cell delay = 3.205 ns ( 47.56 % )
        Info: Total interconnect delay = 3.534 ns ( 52.44 % )
Info: th for memory "lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3" (data pin = "rdaddress[3]", clock pin = "clock") is 0.286 ns
    Info: + Longest clock path from clock "clock" to destination memory is 2.988 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.831 ns) + CELL(0.878 ns) = 2.988 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3'
        Info: Total cell delay = 2.018 ns ( 67.54 % )
        Info: Total interconnect delay = 0.970 ns ( 32.46 % )
    Info: + Micro hold delay of destination is 0.267 ns
    Info: - Shortest pin to memory delay is 2.969 ns
        Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_131; Fanout = 1; PIN Node = 'rdaddress[3]'
        Info: 2: + IC(1.643 ns) + CELL(0.176 ns) = 2.969 ns; Loc. = M4K_X27_Y7; Fanout = 8; MEM Node = 'lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0~portb_address_reg3'
        Info: Total cell delay = 1.326 ns ( 44.66 % )
        Info: Total interconnect delay = 1.643 ns ( 55.34 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 113 megabytes of memory during processing
    Info: Processing ended: Sat Aug 23 14:02:28 2008
    Info: Elapsed time: 00:00:00