boot2410.s

HaiBIOS 是为我的S3C2410开发板写的一个启动程序。 C盘是RAMDISK

;---------------------------------------------------------------------------------
; Copyright (c) Haisoft 2007-9-1
; Author:				Kingsea
; Email:				[e-mail]
;-------------------------------------------------------------
; Project:				HaiBios
; File:					boot2410.s
; Description:	Startup Code for ARM920 CPU-core
;-------------------------------------------------------------
; Reversion Histroy:
;-------------------------------------------------------------
; Version		date		operations				by who
; 1.0.0		2007-09-01		Create					Kingsea
;
;---------------------------------------------------------------------------------

;-------------------------------------------------------------
;	included area
;-------------------------------------------------------------
	INCLUDE cfg2410.inc
	INCLUDE memcfg.inc
	INCLUDE reg2410.inc

;-------------------------------------------------------------
;	import area
;-------------------------------------------------------------
	IMPORT			Main

	IMPORT			|Image$$RO$$Base|		; Base of ROM code
	IMPORT			|Image$$RO$$Limit|  	; End of ROM code (=start of ROM data)
	IMPORT			|Image$$RW$$Base|   	; Base of RAM to initialise
	IMPORT			|Image$$ZI$$Base|   	; Base and limit of area
	IMPORT			|Image$$ZI$$Limit|  	; to zero initialise	
	
;-------------------------------------------------------------
;	code area
;-------------------------------------------------------------
	AREA SelfBoot, CODE, READONLY
	
	ENTRY
	
	EXPORT startup
;-------------------------------------------------------------
; Jump vector table
;-------------------------------------------------------------
startup
	b			rst_proc
	ldr		pc, UND_ADDR
	ldr		pc, SWI_ADDR
	ldr		pc, PABT_ADDR
	ldr		pc, DABT_ADDR
	ldr		pc, RSV_ADDR
	ldr		pc, IRQ_ADDR
	ldr		pc, FIQ_ADDR

UND_ADDR		DCD		und_proc
SWI_ADDR		DCD		swi_proc
PABT_ADDR		DCD		pabt_proc
DABT_ADDR		DCD		dabt_proc
RSV_ADDR		DCD		rsv_proc
IRQ_ADDR		DCD		irq_proc
FIQ_ADDR		DCD		fiq_proc
	
;-------------------------------------------------------------
; reset: init cpu and board
;-------------------------------------------------------------
rst_proc
;	mrs		r0, cpsr				;set the cpu to svc32 mode
;	bic		r0, r0, #MODEMSK
;	orr		r0, r0, #SVCMODE
;	msr		cpsr_c, r0

	ldr		r0, =WTCON			;disable watch dog
	mov		r1, #0x00
	str		r1, [r0]
	
	ldr		r0, =INTMSK			;disable all interrupt
	mov		r1, #0xFFFFFFFF
	str		r1, [r0]
	ldr		r0, =INTSUBMSK
	ldr		r1, =0x7FF			;0x3FF
	str		r1, [r0]
	
	ldr		r0, =CLKDIVN		;set cpu division  FCLK:HCLK:PCLK=1:2:4  FCLK=120MHz
	mov		r1, #3
	str		r1, [r0]
	
	ldr		r0,=MPLLCON			;set cpu frequence
	ldr		r1,=MPLLCON_120
	str		r1,[r0]
	
	bl		SetupCP15
	bl		MemoryConfig
	bl		StackSetup
	bl		InitBSS

;----------------------------------------------------------
; some test
;----------------------------------------------------------
;all led display
	ldr		r0, =GPBCON;
	ldr		r1, =0x01		
	str		r1, [r0]
	ldr		r0, =GPBDAT
	ldr		r1, =0x00
	str		r1, [r0]
;	rGPBCON &= ~3;
;	rGPBCON |= 1;		//set GPB0 as output
;	rGPBDAT &= ~1;		//output 0;

;----------------------------------------------------------
; enter c code
;----------------------------------------------------------
	bl		Main
	b		.


und_proc 
swi_proc 
pabt_proc
dabt_proc
rsv_proc 
irq_proc 	
fiq_proc
	b		rst_proc
	
	

SetupCP15
; flush v4 I/D caches
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0			; flush v3/v4 cache
	mcr	p15, 0, r0, c8, c7, 0			; flush v4 TLB
	
; disable MMU stuff and caches
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300				; clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087				; clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002				; set bit 2 (A) Align
	orr	r0, r0, #0x00001000				; set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0

; now return
	mov pc, lr

MemoryConfig	
;Set memory control registers
	adr	r0, SMRDATA					;cant use ldr r0, =xxxx important!!!
	ldr	r1, =BWSCON					;BWSCON Address
	add	r2, r0, #52					;End address of SMRDATA
0       
	ldr	r3, [r0], #4    
	str	r3, [r1], #4    
	cmp	r2, r0		
	bne	%B0
	
	mov pc, lr
	
StackSetup
	;TODO:
;	mrs		r0, cpsr				;set the cpu to svc32 mode
;	bic		r0, r0, #MODEMSK|NONEINT
;	orr		r0, r0, #SVCMODE
;	msr		cpsr_cxsf, r0
	ldr sp, =STACK_BASEADDR
	mov pc, lr
	
InitBSS
	ldr		r0, TopOfROM
	ldr		r1, BaseOfBSS
	ldr		r3, BaseOfZero  
	
	cmp		r0, r1      ; Check that they are different
	beq		%F2
1       
	cmp		r1, r3      ; Copy init data
	ldrcc	r2, [r0], #4    ;--> LDRCC r2, [r0] + ADD r0, r0, #4         
	strcc	r2, [r1], #4    ;--> STRCC r2, [r1] + ADD r1, r1, #4
	bcc		%B1
2       
	ldr		r1, EndOfBSS
	mov		r2, #0
3       
	cmp		r3, r1      ; Zero init
	strcc	r2, [r3], #4
	bcc		%B3

	mov		pc, lr
	
;------------------------------------------------------------
; code end and data begin
;------------------------------------------------------------
	LTORG

SMRDATA DATA
; Memory configuration should be optimized for best performance 
; The following parameter is not optimized.                     
; Memory access cycle parameter strategy
; 1) The memory settings is  safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK=75Mhz. 

    	DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
    	DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0
    	DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1 
    	DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2
    	DCD 0x1f7c;((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3
    	DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4
    	DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5
    	DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    ;GCS6
    	DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    ;GCS7
    	DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)    
;    	DCD 0x30            ;SCLK power saving mode, BANKSIZE 32M/32M
    	DCD 0x32            ;SCLK power saving mode, BANKSIZE 128M/128M
    	DCD 0x30            ;MRSR6 CL=3clk
    	DCD 0x30            ;MRSR7
;    	DCD 0x20            ;MRSR6 CL=2clk
;    	DCD 0x20            ;MRSR7

BaseOfROM			DCD	|Image$$RO$$Base|
TopOfROM			DCD	|Image$$RO$$Limit|
BaseOfBSS			DCD	|Image$$RW$$Base|
BaseOfZero			DCD	|Image$$ZI$$Base|
EndOfBSS			DCD	|Image$$ZI$$Limit|


 	END