stp1.stp

对ad0804的控制工程

<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP2C8 (0x020B20DD)" sof_file="ad0804.sof" top_level_entity="ad0804">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <global_info>
    <multi attribute="window position" size="9" value="803,498,398,124,356,50,60,0,1"/>
    <single attribute="active instance" value="0"/>
    <single attribute="lock mode" value="36110"/>
  </global_info>
  <instance compilation_mode="full" entity_name="sld_signaltap" is_auto_node="yes" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
    <position_info>
      <single attribute="active tab" value="1"/>
      <single attribute="setup vertical scroll position" value="0"/>
      <single attribute="setup horizontal scroll position" value="0"/>
    </position_info>
    <signal_set global_temp="1" name="signal_set: 2008/10/15 17:54:49  #0">
      <clock name="clk" polarity="posedge" tap_mode="probeonly"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="4096" trigger_in_enable="no" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="ALE" tap_mode="classic" type="output pin"/>
          <wire name="OE" tap_mode="classic" type="output pin"/>
          <wire name="START" tap_mode="classic" type="output pin"/>
          <wire name="rst_n" tap_mode="classic" type="input pin"/>
          <wire name="scl" tap_mode="classic" type="output pin"/>
          <wire name="EOC" tap_mode="probeonly" type="input pin"/>
          <wire name="d1" tap_mode="probeonly" type="input pin"/>
          <wire name="d2" tap_mode="probeonly" type="input pin"/>
          <wire name="d3" tap_mode="probeonly" type="input pin"/>
          <wire name="d4" tap_mode="probeonly" type="input pin"/>
          <wire name="d5" tap_mode="probeonly" type="input pin"/>
          <wire name="d6" tap_mode="probeonly" type="input pin"/>
          <wire name="d7" tap_mode="probeonly" type="input pin"/>
          <wire name="d8" tap_mode="probeonly" type="input pin"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="ALE" tap_mode="classic" type="output pin"/>
          <wire name="OE" tap_mode="classic" type="output pin"/>
          <wire name="START" tap_mode="classic" type="output pin"/>
          <wire name="rst_n" tap_mode="classic" type="input pin"/>
          <wire name="scl" tap_mode="classic" type="output pin"/>
          <wire name="EOC" tap_mode="probeonly" type="input pin"/>
          <wire name="d1" tap_mode="probeonly" type="input pin"/>
          <wire name="d2" tap_mode="probeonly" type="input pin"/>
          <wire name="d3" tap_mode="probeonly" type="input pin"/>
          <wire name="d4" tap_mode="probeonly" type="input pin"/>
          <wire name="d5" tap_mode="probeonly" type="input pin"/>
          <wire name="d6" tap_mode="probeonly" type="input pin"/>
          <wire name="d7" tap_mode="probeonly" type="input pin"/>
          <wire name="d8" tap_mode="probeonly" type="input pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <net is_signal_inverted="no" name="EOC"/>
          <net is_signal_inverted="no" name="d1"/>
          <net is_signal_inverted="no" name="d2"/>
          <net is_signal_inverted="no" name="d3"/>
          <net is_signal_inverted="no" name="d4"/>
          <net is_signal_inverted="no" name="d5"/>
          <net is_signal_inverted="no" name="d6"/>
          <net is_signal_inverted="no" name="d7"/>
          <net is_signal_inverted="no" name="d8"/>
          <net is_signal_inverted="no" name="ALE"/>
          <net is_signal_inverted="no" name="OE"/>
          <net is_signal_inverted="no" name="START"/>
          <net is_signal_inverted="no" name="rst_n"/>
          <net is_signal_inverted="no" name="scl"/>
        </data_view>
        <setup_view>
          <net is_signal_inverted="no" name="EOC"/>
          <net is_signal_inverted="no" name="d1"/>
          <net is_signal_inverted="no" name="d2"/>
          <net is_signal_inverted="no" name="d3"/>
          <net is_signal_inverted="no" name="d4"/>
          <net is_signal_inverted="no" name="d5"/>
          <net is_signal_inverted="no" name="d6"/>
          <net is_signal_inverted="no" name="d7"/>
          <net is_signal_inverted="no" name="d8"/>
          <net is_signal_inverted="no" name="ALE"/>
          <net is_signal_inverted="no" name="OE"/>
          <net is_signal_inverted="no" name="START"/>
          <net is_signal_inverted="no" name="rst_n"/>
          <net is_signal_inverted="no" name="scl"/>
        </setup_view>
      </presentation>
      <trigger global_temp="1" name="trigger: 2008/10/15 17:54:49  #1" position="pre" power_up_trigger_mode="false" segment_size="1" trigger_in="dont_care" trigger_out="active high" trigger_type="circular">
        <power_up_trigger position="pre" trigger_in="dont_care" trigger_out="active high"/>
        <events use_custom_flow_control="no">
          <level enabled="yes" name="condition1" type="basic">
            <power_up enabled="yes">
            </power_up>
            <op_node/>
          </level>
        </events>
        <log>
          <data global_temp="1" name="log: 2008/10/15 17:54:49  #2"/>
          <extradata/>
        </log>
      </trigger>
    </signal_set>
  </instance>
  <mnemonics/>
</session>