📄 mic.mdl
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IncDataTypeInIds off
MangleLength 1
CustomSymbolStrGlobalVar "$R$N$M"
CustomSymbolStrType "$N$R$M"
CustomSymbolStrField "$N$M"
CustomSymbolStrFcn "$R$N$M$F"
CustomSymbolStrBlkIO "rtb_$N$M"
CustomSymbolStrTmpVar "$N$M"
CustomSymbolStrMacro "$R$N$M"
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
SimulinkBlockComments on
EnableCustomComments off
InlinedPrmAccess "Literals"
ReqsInCode off
}
Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 10
Array {
Type "Cell"
Dimension 15
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "GenerateTestInterfaces"
Cell "ModelStepFunctionPrototypeControlCompliant"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
Cell "PortableWordSizes"
PropName "DisabledProps"
}
Version "1.3.0"
TargetFcnLib "ansi_tfl_table_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
GenFloatMathFcnCalls "ANSI_C"
UtilityFuncGeneration "Auto"
GenerateFullHeader on
GenerateSampleERTMain off
GenerateTestInterfaces off
IsPILTarget off
ModelReferenceCompliant on
CompOptLevelCompliant on
IncludeMdlTerminateFcn on
CombineOutputUpdateFcns off
SuppressErrorStatus off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
EnableShiftOperators on
ParenthesesLevel "Nominal"
PortableWordSizes off
ModelStepFunctionPrototypeControlCompliant off
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
ExtModeIntrfLevel "Level1"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
hdlcoderui.hdlcc {
$ObjectID 11
Description "HDL Coder custom configuration component"
Version "1.3.0"
Name "HDL Coder"
Array {
Type "Cell"
Dimension 1
Cell ""
PropName "HDLConfigFile"
}
HDLCActiveTab "0"
}
PropName "Components"
}
Name "Configuration"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType DataTypeConversion
OutMin "[]"
OutMax "[]"
OutDataTypeMode "Inherit via back propagation"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
LockScale off
ConvertRealWorld "Real World Value (RWV)"
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
OutMin "[]"
OutMax "[]"
DataType "auto"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
OutMin "[]"
OutMax "[]"
DataType "auto"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "mic"
Location [136, 310, 907, 689]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Bit to Integer\nConverter"
Ports [1, 1]
Position [585, 53, 665, 97]
SourceBlock "commutil2/Bit to Integer\nConverter"
SourceType "Bit to Integer Converter"
nbits "3"
outDtype "Same as input"
}
Block {
BlockType Reference
Name "From Audio\nDevice"
Ports [0, 1]
Position [50, 54, 105, 106]
DialogController "dspDDGCreate"
DialogControllerArgs "DataTag0"
SourceBlock "dspsrcs4/From Audio\nDevice"
SourceType "From Audio Device"
deviceName "Default"
numChannels "1"
sampleRate "44100"
deviceDatatype "Determine from output data type"
autoBufferSize on
bufferSize "4096"
queueDuration "1.0"
frameSize "1024"
outputDatatype "single"
}
Block {
BlockType Reference
Name "Integer to Bit\nConverter"
Ports [1, 1]
Position [285, 178, 365, 222]
SourceBlock "commutil2/Integer to Bit\nConverter"
SourceType "Integer to Bit Converter"
nbits "3"
outDtype "Same as input"
}
Block {
BlockType Reference
Name "Quantizing\nDecoder"
Ports [1, 1]
Position [625, 172, 715, 218]
SourceBlock "commsrccod2/Quantizing\nDecoder"
SourceType "Quantizing Decoder"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
codebook "[-.825 -.5 0, .5 .825]"
QuDType "double"
}
Block {
BlockType Reference
Name "Quantizing\nEncoder"
Ports [1, 2]
Position [165, 24, 255, 66]
SourceBlock "commsrccod2/Quantizing\nEncoder"
SourceType "Quantizing Encoder"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
partition "[-.75 -.25 .25 .75]"
codebook "[-.825 -.5 0 .5 .825]"
idxDType "double"
}
Block {
BlockType Reference
Name "To Audio\nDevice"
Ports [1]
Position [650, 284, 705, 336]
DialogController "dspDDGCreate"
DialogControllerArgs "DataTag1"
SourceBlock "dspsnks4/To Audio\nDevice"
SourceType "To Audio Device"
deviceName "Default"
inheritSampleRate on
sampleRate "44100"
deviceDatatype "Determine from input data type"
autoBufferSize on
bufferSize "4096"
queueDuration "1.0"
}
Line {
SrcBlock "From Audio\nDevice"
SrcPort 1
Points [0, -35]
DstBlock "Quantizing\nEncoder"
DstPort 1
}
Line {
SrcBlock "Quantizing\nEncoder"
SrcPort 1
Points [120, 0; 0, 55; -110, 0]
DstBlock "Integer to Bit\nConverter"
DstPort 1
}
Line {
SrcBlock "Integer to Bit\nConverter"
SrcPort 1
Points [190, 0; 0, -125]
DstBlock "Bit to Integer\nConverter"
DstPort 1
}
Line {
SrcBlock "Bit to Integer\nConverter"
SrcPort 1
Points [0, 85; -60, 0]
DstBlock "Quantizing\nDecoder"
DstPort 1
}
Line {
SrcBlock "Quantizing\nDecoder"
SrcPort 1
Points [0, 80; -85, 0]
DstBlock "To Audio\nDevice"
DstPort 1
}
}
}
MatData {
NumRecords 2
DataRecord {
Tag DataTag1
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DataRecord {
Tag DataTag0
Data " %)30 . N 8 ( 0 % \" $ \" 0 . 0 8 ( ! % \" $ / 0 0 #P $9R;VU!=61I;T1E=FEC90 . 0 8 ( ! % \" $ ) 0 0 \"0 &1S<&1I86QO9P "
}
}
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