opcode list.info

可以输入PC下编译的软件

0F 4E /r	CMOVLE r32,r/m32	Move if less or equal (ZF=1 or SF<>OF)
0F 46 /r	CMOVNA r16,r/m16	Move if not above (CF=1 or ZF=1)
0F 46 /r	CMOVNA r32,r/m32	Move if not above (CF=1 or ZF=1)
0F 42 /r	CMOVNAE r16,r/m16	Move if not above or equal (CF=1)
0F 42 /r	CMOVNAE r32,r/m32	Move if not above or equal (CF=1)
0F 43 /r	CMOVNB r16,r/m16	Move if not below (CF=0)
0F 43 /r	CMOVNB r32,r/m32	Move if not below (CF=0)
0F 47 /r	CMOVNBE r16,r/m16	Move if not below or equal (CF=0 and ZF=0)
0F 47 /r	CMOVNBE r32,r/m32	Move if not below or equal (CF=0 and ZF=0)
0F 43 /r	CMOVNC r16,r/m16	Move if not carry (CF=0)
0F 43 /r	CMOVNC r32,r/m32	Move if not carry (CF=0)
0F 45 /r	CMOVNE r16,r/m16	Move if not equal (ZF=0)
0F 45 /r	CMOVNE r32,r/m32	Move if not equal (ZF=0)
0F 4E /r	CMOVNG r16,r/m16	Move if not greater (ZF=1 or SF<>OF)
0F 4E /r	CMOVNG r32,r/m32	Move if not greater (ZF=1 or SF<>OF)
0F 4C /r	CMOVNGE r16,r/m16	Move if not greater or equal (SF<>OF)
0F 4C /r	CMOVNGE r32,r/m32	Move if not greater or equal (SF<>OF)
0F 4D /r	CMOVNL r16,r/m16	Move if not less (SF=OF)
0F 4D /r	CMOVNL r32,r/m32	Move if not less (SF=OF)
0F 4F /r	CMOVNLE r16,r/m16	Move if not less or equal (ZF=0 and SF=OF)
0F 4F /r	CMOVNLE r32,r/m32	Move if not less or equal (ZF=0 and SF=OF)
0F 41 /r	CMOVNO r16,r/m16	Move if not overflow (OF=0)
0F 41 /r	CMOVNO r32,r/m32	Move if not overflow (OF=0)
0F 4B /r	CMOVNP r16,r/m16	Move if not parity (PF=0)
0F 4B /r	CMOVNP r32,r/m32	Move if not parity (PF=0)
0F 49 /r	CMOVNS r16,r/m16	Move if not sign (SF=0)
0F 49 /r	CMOVNS r32,r/m32	Move if not sign (SF=0)
0F q5 /r	CMOVNZ r16,r/m16	Move if not zero (ZF=0)
0F 45 /r	CMOVNZ r32,r/m32	Move if not zero (ZF=0)
0F 40 /r	CMOVO r16,r/m16	Move if overflow (OF=1)
0F 40 /r	CMOVO r32,r/m32	Move if overflow (OF=1)
0F 4A /r	CMOVP r16,r/m16	Move if parity (PF=1)
0F 4A /r	CMOVP r32,r/m32	Move if parity (PF=1)
0F 4A /r	CMOVPE r16,r/m16	Move if parity even (PF=1)
0F 4A /r	CMOVPE r32,r/m32	Move if parity even (PF=1)
0F 4B /r	CMOVPO r16,r/m16	Move if parity odd (PF=0)
0F 4B /r	CMOVPO r32,r/m32	Move if parity odd (PF=0)
0F 48 /r	CMOVS r16,r/m16	Move if sign (SF=1)
0F 48 /r	CMOVS r32,r/m32	Move if sign (SF=1)
0F 44 /r	CMOVZ r16,r/m16	Move if zero (ZF=1)
0F 44 /r	CMOVZ r32,r/m32	Move if zero (ZF=1)
3C ib	CMP AL,imm8	Compare imm8 with AL
3D iw	CMP AX,imm16	Compare imm16 with AX
3D id	CMP EAX,imm32	Compare imm32 with EAX
80 /7 ib	CMP r/m8,imm8	Compare imm8 with r/m8
81 /7 iw	CMP r/m16,imm16	Compare imm16 with r/m16
81 /7 id	CMP r/m32,imm32	Compare imm32 with r/m32
83 /7 ib	CMP r/m16,imm8	Compare imm8 with r/m16
83 /7 ib	CMP r/m32,imm8	Compare imm8 with r/m32
38 /r	CMP r/m8,r8	Compare r8 with r/m8
39 /r	CMP r/m16,r16	Compare r16 with r/m16
39 /r	CMP r/m32,r32	Compare r32 with r/m32
3A /r	CMP r8,r/m8	Compare r/m8 with r8
3B /r	CMP r16,r/m16	Compare r/m16 with r16
3B /r	CMP r32,r/m32	Compare r/m32 with r32
66 0F C2 /r ib	CMPPD xmm1,xmm2/m128,imm8	Compare packed double-precision floatingpointvalues in xmm2/m128 and xmm1 usingimm8 as comparison predicate.
0F C2 /r ib	CMPPS xmm1,xmm2/m128,imm8	Compare packed single-precision floating-pointvalues in xmm2/mem and xmm1 using imm8 ascomparison predicate.
A6	CMPS m8,m8	Compares byte at address DS:(E)SI with byte at address ES:(E)DI and sets the status flags accordingly
A7	CMPS m16,m16	Compares word at address DS:(E)SI with word at addressES:(E)DI and sets the status flags accordingly
A7	CMPS m32,m32	Compares doubleword at address DS:(E)SI with doublewordat address ES:(E)DI and sets the status flags accordingly
A6	CMPSB	Compares byte at address DS:(E)SI with byte at addressES:(E)DI and sets the status flags accordingly
A7	CMPSW	Compares word at address DS:(E)SI with word at addressES:(E)DI and sets the status flags accordingly
A7	CMPSD	Compares doubleword at address DS:(E)SI with doublewordat address ES:(E)DI and sets the status flags accordingly
F2 0F C2 /r ib	CMPSD xmm1,xmm2/m64,imm8	Compare low double-precision floating-pointvalue in xmm2/m64 and xmm1 using imm8 ascomparison predicate.
F3 0F C2 /r ib	CMPSS xmm1,xmm2/m32,imm8	Compare low single-precision floating-pointvalue in xmm2/m32 and xmm1 using imm8 ascomparison predicate.
0F B0 /r	CMPXCHG r/m8,r8	Compare AL with r/m8. If equal, ZF is set and r8 is loadedinto r/m8. Else, clear ZF and load r/m8 into AL.
0F B1 /r	CMPXCHG r/m16,r16	Compare AX with r/m16. If equal, ZF is set and r16 isloaded into r/m16. Else, clear ZF and load r/m16 into AX
0F B1 /r	CMPXCHG r/m32,r32	Compare EAX with r/m32. If equal, ZF is set and r32 isloaded into r/m32. Else, clear ZF and load r/m32 into EAX
0F C7 /1 m64	CMPXCHG8B m64	Compare EDX:EAX with m64. If equal, set ZF and loadECX:EBX into m64. Else, clear ZF and load m64 intoEDX:EAX.
66 0F 2F /r	COMISD xmm1,xmm2/m64	Compare low double-precision floating-point values inxmm1 and xmm2/mem64 and set the EFLAGS flagsaccordingly.
0F 2F /r	COMISS xmm1,xmm2/m32	Compare low single-precision floating-point values inxmm1 and xmm2/mem32 and set the EFLAGS flagsaccordingly.
0F A2	CPUID	Returns processor identification and feature informationto the EAX, EBX, ECX, and EDX registers, according tothe input value entered initially in the EAX register
F3 0F E6	CVTDQ2PD xmm1,xmm2/m64	Convert two packed signed doubleword integers fromxmm2/m128 to two packed double-precision floatingpointvalues in xmm1.
0F 5B /r	CVTDQ2PS xmm1,xmm2/m128	Convert four packed signed doubleword integersfrom xmm2/m128 to four packed single-precisionfloating-point values in xmm1.
F2 0F E6	CVTPD2DQ xmm1,xmm2/m128	Convert two packed double-precision floating-pointvalues from xmm2/m128 to two packed signeddoubleword integers in xmm1.
66 0F 2D /r	CVTPD2PI mm,xmm/m128	Convert two packed double-precision floating-pointvalues from xmm/m128 to two packed signeddoubleword integers in mm.
66 0F 5A /r	CVTPD2PS xmm1,xmm2/m128	Convert two packed double-precision floating-pointvalues in xmm2/m128 to two packed singleprecisionfloating-point values in xmm1.
66 0F 2A /r	CVTPI2PD xmm,mm/m64	Convert two packed signed doubleword integers frommm/mem64 to two packed double-precision floating-pointvalues in xmm.
0F 2A /r	CVTPI2PS xmm,mm/m64	Convert two signed doubleword integers from mm/m64 to twosingle-precision floating-point values in xmm.
66 0F 5B /r	CVTPS2DQ xmm1,xmm2/m128	Convert four packed single-precision floatingpointvalues from xmm2/m128 to four packedsigned doubleword integers in xmm1.
0F 5A /r	CVTPS2PD xmm1,xmm2/m64	Convert two packed single-precision floating-pointvalues in xmm2/m64 to two packed double-precisionfloating-point values in xmm1.
0F 2D /r	CVTPS2PI mm,xmm/m64	Convert two packed single-precision floating-point valuesfrom xmm/m64 to two packed signed doublewordintegers in mm.
F2 0F 2D /r	CVTSD2SI r32,xmm/m64	Convert one double-precision floating-point value fromxmm/m64 to one signed doubleword integer r32.
F2 0F 5A /r	CVTSD2SS xmm1,xmm2/m64	Convert one double-precision floating-point value inxmm2/m64 to one single-precision floating-pointvalue in xmm1.
F2 0F 2A /r	CVTSI2SD xmm,r/m32	Convert one signed doubleword integer from r/m32 to onedouble-precision floating-point value in xmm.
F3 0F 2A /r	CVTSI2SS xmm,r/m32	Convert one signed doubleword integer from r/m32 to onesingle-precision floating-point value in xmm.
F3 0F 5A /r	CVTSS2SD xmm1,xmm2/m32	Convert one single-precision floating-point value inxmm2/m32 to one double-precision floating-pointvalue in xmm1.
F3 0F 2D /r	CVTSS2SI r32,xmm/m32	Convert one single-precision floating-point value fromxmm/m32 to one signed doubleword integer in r32.
66 0F 2C /r	CVTTPD2PI mm,xmm/m128	Convert two packer double-precision floating-pointvalues from xmm/m128 to two packed signeddoubleword integers in mm using truncation.
66 0F E6	CVTTPD2DQ xmm1,xmm2/m128	Convert two packed double-precision floating-pointvalues from xmm2/m128 to two packed signeddoubleword integers in xmm1 using truncation.
F3 0F 5B /r	CVTTPS2DQ xmm1,xmm2/m128	Convert four single-precision floating-pointvalues from xmm2/m128 to four signeddoubleword integers in xmm1 using truncation.
0F 2C /r	CVTTPS2PI mm,xmm/m64	Convert two single-precision floating-point values fromxmm/m64 to two signed doubleword signed integers inmm using truncation.
F2 0F 2C /r	CVTTSD2SI r32,xmm/m64	Convert one double-precision floating-point value fromxmm/m64 to one signed doubleword integer in r32 usingtruncation.
F3 0F 2C /r	CVTTSS2SI r32,xmm/m32	Convert one single-precision floating-point value fromxmm/m32 to one signed doubleword integer in r32 usingtruncation.
99	CWD	DX:AX = sign-extend of AX
99	CDQ	EDX:EAX = sign-extend of EAX
27	DAA	Decimal adjust AL after addition
2F	DAS	Decimal adjust AL after subtraction
FE /1	DEC r/m8	Decrement r/m8 by 1
FF /1	DEC r/m16	Decrement r/m16 by 1
FF /1	DEC r/m32	Decrement r/m32 by 1
;48 +rw	DEC r16	Decrement r16 by 1
;48 +rd	DEC r32	Decrement r32 by 1
48	DEC EAX	Decrement r32 by 1
49	DEC ECX	Decrement r32 by 1
4A	DEC EDX	Decrement r32 by 1
4B	DEC EBX	Decrement r32 by 1
4C	DEC ESP	Decrement r32 by 1
4D	DEC EBP	Decrement r32 by 1
4E	DEC ESI	Decrement r32 by 1
4F	DEC EDI	Decrement r32 by 1
F6 /6	DIV r/m8	Unsigned divide AX by r/m8, with result stored inAL = Quotient, AH = Remainder
F7 /6	DIV r/m16	Unsigned divide DX:AX by r/m16, with result stored inAX = Quotient, DX = Remainder
F7 /6	DIV r/m32	Unsigned divide EDX:EAX by r/m32, with result stored inEAX = Quotient, EDX = Remainder
66 0F 5E /r	DIVPD xmm1,xmm2/m128	Divide packed double-precision floating-point values inxmm1 by packed double-precision floating-point valuesxmm2/m128.
0F 5E /r	DIVPS xmm1,xmm2/m128	Divide packed single-precision floating-point values inxmm1 by packed single-precision floating-point valuesxmm2/m128.
F2 0F 5E /r	DIVSD xmm1,xmm2/m64	Divide low double-precision floating-point value n xmm1by low double-precision floating-point value inxmm2/mem64.
F3 0F 5E /r	DIVSS xmm1,xmm2/m32	Divide low single-precision floating-point value in xmm1by low single-precision floating-point value inxmm2/m32
0F 77	EMMS	Set the x87 FPU tag word to empty.
C8 iw 00	ENTER imm16,0	Create a stack frame for a procedure
C8 iw 01	ENTER imm16,1	Create a nested stack frame for a procedure
C8 iw ib	ENTER imm16,imm8	Create a nested stack frame for a procedure
D9 F0	F2XM1	Replace ST(0) with (2ST(0)