📄 syslib.c
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/* sysLib.c - AT91RM9200 CSB337 system-dependent routines */
/* Copyright 2004 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
modification history
--------------------
01a,13sep04,pdr based on template.
*/
/*
DESCRIPTION
This library provides board-specific routines. The chip drivers included are:
at91Timer.c - AT91 timer driver
at91Sio.c - AT91 SIO driver
at91Timer.c - timer library (system/auxiliary/timestamp clock)
flashMem.c - generic flash library
nvRamToFlash.c - byte-oriented generic non-volatile RAM library
nullVme.c - null VMEbus library
at91IntrCtl.c - AT91RM9200 interrrupt controller device
at91EmacEnd.c - AT91RM9200 END driver
INCLUDE FILES: sysLib.h
SEE ALSO:
.pG "Configuration"
.I "ARM Architecture Reference Manual,"
.I "ARM 920T Technical Reference Manual",
.I "Cogent CSB337 Atmel AT91RM9200 OEM Single Board Computer, Hardware Reference Manual".
*/
/* includes */
#include "vxWorks.h"
#include "config.h"
#include "sysLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "muxLib.h"
#include "cacheLib.h"
#include "arch/arm/mmuArmLib.h"
#include "private/vmLibP.h"
#include "dllLib.h"
#include "wdLib.h"
#include "drv/usb/usbOhci.h"
/* imports */
IMPORT char end []; /* end of system, created by ld */
IMPORT VOIDFUNCPTR _func_armIntStackSplit; /* ptr to fn to split stack */
#if !defined(INCLUDE_MMU) && \
(defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU_BASIC) || \
defined(INCLUDE_MMU_FULL) || defined(INCLUDE_MMU_MPU))
#define INCLUDE_MMU
#endif
/* globals */
#if defined(INCLUDE_MMU)
/*
* The following structure describes the various different parts of the
* memory map to be used only during initialisation by
* vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC/FULL are
* defined.
*
* Clearly, this structure is only needed if the CPU has an MMU!
*
* The following are not the smallest areas that could be allocated for a
* working system. If the amount of memory used by the page tables is
* critical, they could be reduced.
*/
PHYS_MEM_DESC sysPhysMemDesc [] =
{
/* Internal Memory (SRAM, ROM, USB Host, or tightly-coupled memory) */
{
(void *) 0, /* virtual address */
(void *) 0, /* physical address */
SZ_4M, /* length, then initial state */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
/*
* Flash memory: marked valid and writeable but not cached -
* we need to be able to poll words in the Flash when updating
* contents.
*/
{
(void *) ROM_BASE_ADRS, /* virtual address */
(void *) ROM_BASE_ADRS, /* physical address */
ROM_SIZE, /* length */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
},
/*
* Map the peripheral register area as writable but not cached or
* buffered.
*/
{
(void *) CSB337_PERIPHERAL_BASE, /* virtual address */
(void *) CSB337_PERIPHERAL_BASE, /* physical address */
CSB337_PERIPHERAL_SIZE, /* length */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
}
};
int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);
#endif /* defined(INCLUDE_MMU) */
int sysBus = BUS; /* system bus type (VME_BUS, etc) */
int sysCpu = CPU; /* system CPU type (e.g. ARMARCH4/4_T)*/
char * sysBootLine = BOOT_LINE_ADRS; /* address of boot line */
char * sysExcMsg = EXC_MSG_ADRS; /* catastrophic message area */
int sysProcNum; /* processor number of this CPU */
int sysFlags; /* boot flags */
char sysBootHost [BOOT_FIELD_LEN]; /* name of host from which we booted */
char sysBootFile [BOOT_FIELD_LEN]; /* name of file from which we booted */
#ifdef INCLUDE_HEART_BEAT
WDOG_ID sysHeartBeatWdId = NULL; /* heart beat */
#endif /* INCLUDE_HEART_BEAT */
/* locals */
typedef struct _SYS_PERIPHERAL_ELEMENT
{
VOIDFUNCPTR func; /* function to call */
int arg; /* argument passed */
BOOL enabled; /* interrupt enabled */
UINT32 regStatus; /* address of status register */
UINT32 regMask; /* address of mask register */
} SYS_PERIPHERAL_ELEMENT;
LOCAL SYS_PERIPHERAL_ELEMENT sysPeripheralHandlerTbl[SP_MAX_ID] = {
/* RTC */ { NULL, 0, FALSE, (RTC_BASE + RTC_SR) , (RTC_BASE + RTC_IMR)},
/* ST */ { NULL, 0, FALSE, (ST_BASE + ST_SR) , (ST_BASE + ST_IMR)},
/* DBGU */ { NULL, 0, FALSE, (DBGU_BASE + DBGU_SR) , (DBGU_BASE + DBGU_IMR)},
/* PMC */ { NULL, 0, FALSE, (PMC_BASE + PMC_SR) , (PMC_BASE + PMC_IMR)},
/* MC */ { NULL, 0, FALSE, (SDRAMC_BASE + SDRAMC_ISR), (SDRAMC_BASE + SDRAMC_IMR)} /* use SDRAMC registers */
};
/* defines */
/* externals */
IMPORT int at91IntDevInit (void);
IMPORT void sysIntStackSplit (char *, long);
/* globals */
/* forward LOCAL functions declarations */
/* forward declarations */
IMPORT char * sysPhysMemTop (void);
IMPORT void sysHeartBeat (void);
/* system peripheral interrupt utilities */
IMPORT void sysPeripheralIntHandler (void);
IMPORT STATUS sysPeripheralIntConnect (int sysPeripheralId, VOIDFUNCPTR routine, int arg);
IMPORT STATUS sysPeripheralIntEnable (int sysPeripheralId);
IMPORT STATUS sysPeripheralIntDisable (int sysPeripheralId);
/* included source files */
#include "vme/nullVme.c"
#if (NV_RAM_SIZE == NONE)
#include "mem/nullNvRam.c"
#else
#include "flashMem.c"
#include "nvRamToFlash.c"
#ifdef INCLUDE_FLASH_LOADER
#include "sysFlashLoader.c"
#endif /* INCLUDE_FLASH_LOADER */
#endif /* (NV_RAM_SIZE == NONE) */
#include "at91IntrCtl.c"
#include "at91Timer.c"
#if defined(INCLUDE_NETWORK) && defined(INCLUDE_END)
#include "sysEnd.c"
#endif /* INCLUDE_NETWORK && INCLUDE_END */
#ifdef INCLUDE_SERIAL
#include "sysSerial.c"
#else
SIO_CHAN * sysSerialChanGet( int channel )
{
return((SIO_CHAN *) ERROR);
}
#endif /* INCLUDE_SERIAL */
/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* NOTE
* This routine does not include all of the possible variants, and the
* inclusion of a variant in here does not mean that it is supported.
*
* RETURNS: A pointer to a string identifying the board and CPU.
*/
char *sysModel (void)
{
return ("CSB337 - Atmel AT91RM9200 (ARM)");
}
/*******************************************************************************
*
* sysBspRev - return the BSP version with the revision eg 1.2/<x>
*
* This function returns a pointer to a BSP version with the revision.
* e.g. 1.2/<x>. BSP_REV is concatenated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/
char * sysBspRev (void)
{
return (BSP_VERSION BSP_REV);
}
/*******************************************************************************
*
* sysHwInit0 - perform early BSP-specific initialisation
*
* This routine performs such BSP-specific initialisation as is necessary before
* the architecture-independent cacheLibInit can be called. It is called
* from usrInit() before cacheLibInit(), before sysHwInit() and before BSS
* has been cleared.
*
* RETURNS: N/A
*/
void sysHwInit0 (void)
{
#ifdef INCLUDE_CACHE_SUPPORT
/*
* Install the appropriate cache library, no address translation
* routines are required for this BSP, as the default memory map has
* virtual and physical addresses the same.
*/
cacheArm920tLibInstall (NULL, NULL);
#endif /* INCLUDE_CACHE_SUPPORT */
#if defined(INCLUDE_MMU)
mmuArm920tLibInstall (NULL, NULL);
#endif /* defined(INCLUDE_MMU) */
return;
}
/*******************************************************************************
*
* sysHwInit - initialize the CPU board hardware
*
* This routine initializes various features of the board.
* It is the first board-specific C code executed, and runs with
* interrupts masked in the processor.
* This routine resets all devices to a quiescent state, typically
* by calling driver initialization routines.
*
* NOTE: Because this routine will be called from sysToMonitor, it must
* shutdown all potential DMA master devices. If a device is doing DMA
* at reboot time, the DMA could interfere with the reboot. For devices
* on non-local busses, this is easy if the bus reset or sysFail line can
* be asserted.
*
* NOTE: This routine should not be called directly by the user application.
*
* RETURNS: N/A
*/
void sysHwInit (void)
{
/* install the IRQ/SVC interrupt stack splitting routine */
_func_armIntStackSplit = sysIntStackSplit;
/* switch on all user LEDs */
PIOB_REG(PIO_ODSR) = LED_LEDS_MASK; /* LED configuration */
PIOB_REG(PIO_CODR) = LED_LEDS_MASK;
/*
* Set CPU components in a quiescent state
* -> disable component and interrupts
*/
/* AIC -> see romInit.s and sysALib.s */
/* PMC -> see romInit.s */
/* ST */
ST_REG(ST_WDMR) = 0; /* disable watchdog timer */
ST_REG(ST_IDR) = 0x0000000F;
/* RTC */
RTC_REG(RTC_IDR) = 0x0000001F;
/* DBGU */
DBGU_REG(DBGU_CR) = 0x000000A0;
DBGU_REG(DBGU_IDR) = 0xC0001AFB;
DBGU_REG(PDC_RPR) = 0;
DBGU_REG(PDC_RCR) = 0;
DBGU_REG(PDC_TPR) = 0;
DBGU_REG(PDC_TCR) = 0;
DBGU_REG(PDC_RNPR) = 0;
DBGU_REG(PDC_RNCR) = 0;
DBGU_REG(PDC_TNPR) = 0;
DBGU_REG(PDC_TNCR) = 0;
DBGU_REG(PDC_PTCR) = PDC_RXTDIS | PDC_TXTDIS;
/* PIO -> see romInit.s */
/* SPI */
SPI_REG(SPI_CR) = 0x00000002;
SPI_REG(SPI_IDR) = 0x000000FF;
SPI_REG(PDC_RPR) = 0;
SPI_REG(PDC_RCR) = 0;
SPI_REG(PDC_TPR) = 0;
SPI_REG(PDC_TCR) = 0;
SPI_REG(PDC_RNPR) = 0;
SPI_REG(PDC_RNCR) = 0;
SPI_REG(PDC_TNPR) = 0;
SPI_REG(PDC_TNCR) = 0;
SPI_REG(PDC_PTCR) = PDC_RXTDIS | PDC_TXTDIS;
/* TWI */
TWI_REG(TWI_CR) = 0x00000008;
TWI_REG(TWI_IDR) = 0x000001C7;
/* USART */
USART0_REG(US_CR) = 0x000000A0;
USART0_REG(US_IDR) = 0x000F3FFF;
USART0_REG(PDC_RPR) = 0;
USART0_REG(PDC_RCR) = 0;
USART0_REG(PDC_TPR) = 0;
USART0_REG(PDC_TCR) = 0;
USART0_REG(PDC_RNPR) = 0;
USART0_REG(PDC_RNCR) = 0;
USART0_REG(PDC_TNPR) = 0;
USART0_REG(PDC_TNCR) = 0;
USART0_REG(PDC_PTCR) = PDC_RXTDIS | PDC_TXTDIS;
USART1_REG(US_CR) = 0x000000A0;
USART1_REG(US_IDR) = 0x000F3FFF;
USART1_REG(PDC_RPR) = 0;
USART1_REG(PDC_RCR) = 0;
USART1_REG(PDC_TPR) = 0;
USART1_REG(PDC_TCR) = 0;
USART1_REG(PDC_RNPR) = 0;
USART1_REG(PDC_RNCR) = 0;
USART1_REG(PDC_TNPR) = 0;
USART1_REG(PDC_TNCR) = 0;
USART1_REG(PDC_PTCR) = PDC_RXTDIS | PDC_TXTDIS;
USART2_REG(US_CR) = 0x000000A0;
USART2_REG(US_IDR) = 0x000F3FFF;
USART2_REG(PDC_RPR) = 0;
USART2_REG(PDC_RCR) = 0;
USART2_REG(PDC_TPR) = 0;
USART2_REG(PDC_TCR) = 0;
USART2_REG(PDC_RNPR) = 0;
USART2_REG(PDC_RNCR) = 0;
USART2_REG(PDC_TNPR) = 0;
USART2_REG(PDC_TNCR) = 0;
USART2_REG(PDC_PTCR) = PDC_RXTDIS | PDC_TXTDIS;
USART3_REG(US_CR) = 0x000000A0;
USART3_REG(US_IDR) = 0x000F3FFF;
USART3_REG(PDC_RPR) = 0;
USART3_REG(PDC_RCR) = 0;
USART3_REG(PDC_TPR) = 0;
USART3_REG(PDC_TCR) = 0;
USART3_REG(PDC_RNPR) = 0;
USART3_REG(PDC_RNCR) = 0;
USART3_REG(PDC_TNPR) = 0;
USART3_REG(PDC_TNCR) = 0;
USART3_REG(PDC_PTCR) = PDC_RXTDIS | PDC_TXTDIS;
/* SSC */
SSC0_REG(SSC_CR) = 0x00000202;
SSC0_REG(SSC_IDR) = 0x00000CFF;
SSC0_REG(PDC_RPR) = 0;
SSC0_REG(PDC_RCR) = 0;
SSC0_REG(PDC_TPR) = 0;
SSC0_REG(PDC_TCR) = 0;
SSC0_REG(PDC_RNPR) = 0;
SSC0_REG(PDC_RNCR) = 0;
SSC0_REG(PDC_TNPR) = 0;
SSC0_REG(PDC_TNCR) = 0;
SSC0_REG(PDC_PTCR) = PDC_RXTDIS | PDC_TXTDIS;
SSC1_REG(SSC_CR) = 0x00000202;
SSC1_REG(SSC_IDR) = 0x00000CFF;
SSC1_REG(PDC_RPR) = 0;
SSC1_REG(PDC_RCR) = 0;
SSC1_REG(PDC_TPR) = 0;
SSC1_REG(PDC_TCR) = 0;
SSC1_REG(PDC_RNPR) = 0;
SSC1_REG(PDC_RNCR) = 0;
SSC1_REG(PDC_TNPR) = 0;
SSC1_REG(PDC_TNCR) = 0;
SSC1_REG(PDC_PTCR) = PDC_RXTDIS | PDC_TXTDIS;
SSC2_REG(SSC_CR) = 0x00000202;
SSC2_REG(SSC_IDR) = 0x00000CFF;
SSC2_REG(PDC_RPR) = 0;
SSC2_REG(PDC_RCR) = 0;
SSC2_REG(PDC_TPR) = 0;
SSC2_REG(PDC_TCR) = 0;
SSC2_REG(PDC_RNPR) = 0;
SSC2_REG(PDC_RNCR) = 0;
SSC2_REG(PDC_TNPR) = 0;
SSC2_REG(PDC_TNCR) = 0;
SSC2_REG(PDC_PTCR) = PDC_RXTDIS | PDC_TXTDIS;
/* TC */
TC0_REG(TC_CCR) = 0x00000002;
TC0_REG(TC_IDR) = 0x000000FF;
TC1_REG(TC_CCR) = 0x00000002;
TC1_REG(TC_IDR) = 0x000000FF;
TC2_REG(TC_CCR) = 0x00000002;
TC2_REG(TC_IDR) = 0x000000FF;
TC3_REG(TC_CCR) = 0x00000002;
TC3_REG(TC_IDR) = 0x000000FF;
TC4_REG(TC_CCR) = 0x00000002;
TC4_REG(TC_IDR) = 0x000000FF;
TC5_REG(TC_CCR) = 0x00000002;
TC5_REG(TC_IDR) = 0x000000FF;
/* MCI */
MCI_REG(MCI_CR) = 0x0000000A;
MCI_REG(MCI_IDR) = 0xC07FC0FF;
MCI_REG(PDC_RPR) = 0;
MCI_REG(PDC_RCR) = 0;
MCI_REG(PDC_TPR) = 0;
MCI_REG(PDC_TCR) = 0;
MCI_REG(PDC_RNPR) = 0;
MCI_REG(PDC_RNCR) = 0;
MCI_REG(PDC_TNPR) = 0;
MCI_REG(PDC_TNCR) = 0;
MCI_REG(PDC_PTCR) = PDC_RXTDIS | PDC_TXTDIS;
#ifdef INCLUDE_USB
/* UHP */
/*
* Access to the host can only be performed when the MCK is set
* and UDPCK are generates the required 48 MHz clock
*/
UHP_REG(OHCI_HC_CONTROL) = 0;
UHP_REG(OHCI_HC_COMMAND_STATUS) = OHCI_CS_HCR;
#endif /* INCLUDE_USB */
/* EMAC */
EMAC_REG(EMAC_CTL) = 0;
EMAC_REG(EMAC_IDR) = 0x00000FFF;
EMAC_REG(EMAC_TCR) = 0;
EMAC_REG(EMAC_TAR) = 0;
#ifdef INCLUDE_SERIAL
#endif /* INCLUDE_SERIAL */
}
/*******************************************************************************
*
* sysHwInit2 - additional system configuration and initialization
*
* This routine connects system interrupts and does any additional
* configuration necessary. Note that this is called from
* sysClkConnect() in the timer driver.
*
* RETURNS: N/A
*
*/
void sysHwInit2 (void)
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