at91rm9200.h

vwworks 在 at91rm9200上的bsp配置

/* at91rm9200.h - Atmel AT91 register definition */

/*
modification history
--------------------
01a,09sep04,pdr	 written.
*/

#ifndef __INCat91rm9200h
#define __INCat91rm9200h

#include "bits.h"

/* *****************************************************************************      
 *               BASE ADDRESS DEFINITIONS FOR AT91RM9200                              
 * *****************************************************************************/     
#define AT91C_BASE_SYS       (0xFFFFF000) /* (SYS) Base Address        */             
#define AT91C_BASE_MC        (0xFFFFFF00) /* (MC) Base Address         */             
#define AT91C_BASE_RTC       (0xFFFFFE00) /* (RTC) Base Address        */             
#define AT91C_BASE_ST        (0xFFFFFD00) /* (ST) Base Address         */             
#define AT91C_BASE_PMC       (0xFFFFFC00) /* (PMC) Base Address        */
#define AT91C_BASE_CKGR      (0xFFFFFC20) /* (CKGR) Base Address       */
#define AT91C_BASE_PIOD      (0xFFFFFA00) /* (PIOD) Base Address       */
#define AT91C_BASE_PIOC      (0xFFFFF800) /* (PIOC) Base Address       */
#define AT91C_BASE_PIOB      (0xFFFFF600) /* (PIOB) Base Address       */ 
#define AT91C_BASE_PIOA      (0xFFFFF400) /* (PIOA) Base Address       */ 
#define AT91C_BASE_DBGU      (0xFFFFF200) /* (DBGU) Base Address       */ 
#define AT91C_BASE_PDC_DBGU  (0xFFFFF300) /* (PDC_DBGU) Base Address   */ 
#define AT91C_BASE_AIC       (0xFFFFF000) /* (AIC) Base Address        */ 
#define AT91C_BASE_PDC_SPI   (0xFFFE0100) /* (PDC_SPI) Base Address    */ 
#define AT91C_BASE_SPI       (0xFFFE0000) /* (SPI) Base Address        */ 
#define AT91C_BASE_PDC_SSC2  (0xFFFD8100) /* (PDC_SSC2) Base Address   */ 
#define AT91C_BASE_SSC2      (0xFFFD8000) /* (SSC2) Base Address       */ 
#define AT91C_BASE_PDC_SSC1  (0xFFFD4100) /* (PDC_SSC1) Base Address   */ 
#define AT91C_BASE_SSC1      (0xFFFD4000) /* (SSC1) Base Address       */ 
#define AT91C_BASE_PDC_SSC0  (0xFFFD0100) /* (PDC_SSC0) Base Address   */ 
#define AT91C_BASE_SSC0      (0xFFFD0000) /* (SSC0) Base Address       */ 
#define AT91C_BASE_PDC_US3   (0xFFFCC100) /* (PDC_US3) Base Address    */ 
#define AT91C_BASE_US3       (0xFFFCC000) /* (US3) Base Address        */ 
#define AT91C_BASE_PDC_US2   (0xFFFC8100) /* (PDC_US2) Base Address    */ 
#define AT91C_BASE_US2       (0xFFFC8000) /* (US2) Base Address        */ 
#define AT91C_BASE_PDC_US1   (0xFFFC4100) /* (PDC_US1) Base Address    */ 
#define AT91C_BASE_US1       (0xFFFC4000) /* (US1) Base Address        */ 
#define AT91C_BASE_PDC_US0   (0xFFFC0100) /* (PDC_US0) Base Address    */ 
#define AT91C_BASE_US0       (0xFFFC0000) /* (US0) Base Address        */ 
#define AT91C_BASE_PDC_TWI   (0xFFFB8100) /* (PDC_TWI) Base Address    */ 
#define AT91C_BASE_TWI       (0xFFFB8000) /* (TWI) Base Address        */ 
#define AT91C_BASE_MCI       (0xFFFB4000) /* (MCI) Base Address        */ 
#define AT91C_BASE_UDP       (0xFFFB0000) /* (UDP) Base Address        */ 
#define AT91C_BASE_TC5       (0xFFFA4080) /* (TC5) Base Address        */ 
#define AT91C_BASE_TC4       (0xFFFA4040) /* (TC4) Base Address        */ 
#define AT91C_BASE_TC3       (0xFFFA4000) /* (TC3) Base Address        */ 
#define AT91C_BASE_TCB1      (0xFFFA4080) /* (TCB1) Base Address       */ 
#define AT91C_BASE_TC2       (0xFFFA0080) /* (TC2) Base Address        */ 
#define AT91C_BASE_TC1       (0xFFFA0040) /* (TC1) Base Address        */ 
#define AT91C_BASE_TC0       (0xFFFA0000) /* (TC0) Base Address        */ 
#define AT91C_BASE_TCB0      (0xFFFA0000) /* (TCB0) Base Address       */ 
#define AT91C_BASE_UHP       (0x00300000) /* (UHP) Base Address        */ 
#define AT91C_BASE_EMAC      (0xFFFBC000) /* (EMAC) Base Address       */ 
#define AT91C_BASE_EBI       (0xFFFFFF60) /* (EBI) Base Address        */ 
#define AT91C_BASE_SMC       (0xFFFFFF70) /* (SMC) Base Address       */ 
#define AT91C_BASE_SDRAMC    (0xFFFFFF90) /* (SDRAMC) Base Address       */ 
#define AT91C_BASE_BFC       (0xFFFFFFC0) /* (BFC) Base Address        */ 

/******************************************************************************
 *               MEMORY MAPPING DEFINITIONS FOR AT91RM9200
 ******************************************************************************/
#define AT91C_ISRAM	        (0x00200000)        /* Internal SRAM base address */
#define AT91C_ISRAM_SIZE	(0x00004000)        /* Internal SRAM size in byte (16 Kbyte) */
#define AT91C_IROM 	        (0x00100000)        /* Internal ROM base address */
#define AT91C_IROM_SIZE	    (0x00020000)        /* Internal ROM size in byte (128 Kbyte) */

/*****************************************************************************
 * Advanced Interrupt Controller (AIC)
 *****************************************************************************/

/* Source Mode Register - 32 of them */
#define AIC_SMR_BASE	0xFFFFF000
#define AIC_SMR_REG(x)	*(volatile UINT32 *)(AIC_SMR_BASE + ((x) & 0x1f))

/* Source Vector Register - 32 of them */
#define AIC_SVR_BASE	0xFFFFF080
#define AIC_SVR_REG(x)	*(volatile UINT32 *)(AIC_SVR_BASE + ((x) & 0x1f))

/* Register Offsets */
#define AIC_IVR 	0x100	/* IRQ Vector Register                */
#define AIC_FVR 	0x104	/* FIQ Vector Register                */
#define AIC_ISR 	0x108	/* Interrupt Status Register          */
#define AIC_IPR 	0x10C	/* Interrupt Pending Register         */
#define AIC_IMR 	0x110	/* Interrupt Mask Register            */
#define AIC_CISR 	0x114	/* Core Interrupt Status Register     */
#define AIC_IECR 	0x120	/* Interrupt Enable Command Register  */
#define AIC_IDCR 	0x124	/* Interrupt Disable Command Register */
#define AIC_ICCR 	0x128	/* Interrupt Clear Command Register   */
#define AIC_ISCR 	0x12C	/* Interrupt Set Command Register     */
#define AIC_EOICR 	0x130	/* End of Interrupt Command Register  */
#define AIC_SPU 	0x134	/* Spurious Vector Register           */
#define AIC_DCR 	0x138	/* Debug Control Register (Protect)   */
#define AIC_FFER 	0x140	/* Fast Forcing Enable Register       */
#define AIC_FFDR 	0x144	/* Fast Forcing Disable Register      */
#define AIC_FFSR 	0x148	/* Fast Forcing Status Register       */

/* ========== Register definition for AIC peripheral ========== */
#define AT91C_AIC_ICCR  (AT91C_BASE_AIC + AIC_ICCR)  /* (AIC) Interrupt Clear Command Register      */ 
#define AT91C_AIC_IECR  (AT91C_BASE_AIC + AIC_IECR)  /* (AIC) Interrupt Enable Command Register     */ 
#define AT91C_AIC_SMR   (AIC_SMR_BASE)               /* (AIC) Source Mode Register                  */ 
#define AT91C_AIC_ISCR  (AT91C_BASE_AIC + AIC_ISCR)  /* (AIC) Interrupt Set Command Register        */ 
#define AT91C_AIC_EOICR (AT91C_BASE_AIC + AIC_EOICR) /* (AIC) End of Interrupt Command Register     */ 
#define AT91C_AIC_DCR   (AT91C_BASE_AIC + AIC_DCR)   /* (AIC) Debug Control Register (Protect)      */ 
#define AT91C_AIC_FFER  (AT91C_BASE_AIC + AIC_FFER)  /* (AIC) Fast Forcing Enable Register          */ 
#define AT91C_AIC_SVR   (AIC_SVR_BASE)               /* (AIC) Source Vector Register                */ 
#define AT91C_AIC_SPU   (AT91C_BASE_AIC + AIC_SPU)   /* (AIC) Spurious Vector Register              */ 
#define AT91C_AIC_FFDR  (AT91C_BASE_AIC + AIC_FFDR)  /* (AIC) Fast Forcing Disable Register         */ 
#define AT91C_AIC_FVR   (AT91C_BASE_AIC + AIC_FVR)   /* (AIC) FIQ Vector Register                   */ 
#define AT91C_AIC_FFSR  (AT91C_BASE_AIC + AIC_FFSR)  /* (AIC) Fast Forcing Status Register          */ 
#define AT91C_AIC_IMR   (AT91C_BASE_AIC + AIC_IMR)   /* (AIC) Interrupt Mask Register               */ 
#define AT91C_AIC_ISR   (AT91C_BASE_AIC + AIC_ISR)   /* (AIC) Interrupt Status Register             */ 
#define AT91C_AIC_IVR   (AT91C_BASE_AIC + AIC_IVR)   /* (AIC) IRQ Vector Register                   */ 
#define AT91C_AIC_IDCR  (AT91C_BASE_AIC + AIC_IDCR)  /* (AIC) Interrupt Disable Command Register    */ 
#define AT91C_AIC_CISR  (AT91C_BASE_AIC + AIC_CISR)  /* (AIC) Core Interrupt Status Register        */
#define AT91C_AIC_IPR   (AT91C_BASE_AIC + AIC_IPR)   /* (AIC) Interrupt Pending Register            */

/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ 
#define AT91C_AIC_PRIOR         (0x7) /* (AIC) Priority Level */
#define AT91C_AIC_PRIOR_LOWEST  (0x0) /* (AIC) Lowest priority level */
#define AT91C_AIC_PRIOR_HIGHEST (0x7) /* (AIC) Highest priority level */

#define AT91C_AIC_SRCTYPE                      (0x3) /* (AIC) Interrupt Source Type */
#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0) /* (AIC) Internal Sources Code Label Level Sensitive */
#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1) /* (AIC) Internal Sources Code Label Edge triggered */
#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2) /* (AIC) External Sources Code Label High-level Sensitive */
#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3) /* (AIC) External Sources Code Label Positive Edge triggered */
                                                 
/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ 
#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) /* (AIC) NFIQ Status */
#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) /* (AIC) NIRQ Status */

/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ 
#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) /* (AIC) Protection Mode */
#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) /* (AIC) General Mask */

/* *****************************************************************************
 * Debug Unit (DBGU)
 * *****************************************************************************/
#define DBGU_BASE	0xFFFFF200
#define DBGU_REG(x)	*(volatile UINT32 *)(DBGU_BASE + (x))

/* Register Offsets */
#define DBGU_CR 	0x00	/* Control Register             */
#define DBGU_MR 	0x04	/* Mode Register                */
#define DBGU_IER 	0x08	/* Interrupt Enable Register    */
#define DBGU_IDR 	0x0C	/* Interrupt Disable Register   */
#define DBGU_IMR 	0x10	/* Interrupt Mask Register      */
#define DBGU_SR 	0x14	/* Channel Status Register      */
#define DBGU_RHR 	0x18	/* Receiver Holding Register    */
#define DBGU_THR 	0x1C	/* Transmitter Holding Register */
#define DBGU_BRGR 	0x20	/* Baud Rate Generator Register */
#define DBGU_C1R 	0x40	/* Chip ID1 Register            */
#define DBGU_C2R 	0x44	/* Chip ID2 Register            */
#define DBGU_FNTR 	0x48	/* Force NTRST Register         */
                                                                        
/* *****************************************************************************
 * Peripheral Data Control (DMA)
 * Note that each of the following peripherals has it's own
 * set of these registers starting at offset 0x100 from it's
 * base address: DBGU, SPI, USART and SSC
 * To access the DMA for a peripheral, use the macro for that 
 * peripheral but with these register offsets
 * *****************************************************************************/
/* Register Offsets */
#define PDC_RPR 	0x100	/* Receive Pointer Register          */ 
#define PDC_RCR 	0x104	/* Receive Counter Register          */ 
#define PDC_TPR 	0x108	/* Transmit Pointer Register         */ 
#define PDC_TCR 	0x10c	/* Transmit Counter Register         */ 
#define PDC_RNPR 	0x110	/* Receive Next Pointer Register     */ 
#define PDC_RNCR 	0x114	/* Receive Next Counter Register     */ 
#define PDC_TNPR 	0x118	/* Transmit Next Pointer Register    */ 
#define PDC_TNCR 	0x11c	/* Transmit Next Counter Register    */
#define PDC_PTCR 	0x120	/* PDC Transfer Control Register     */
#define PDC_PTSR 	0x124	/* PDC Transfer Status Register      */

/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
#define PDC_RXTEN       ((unsigned int) 0x1 <<  0) /* (PDC) Receiver Transfer Enable     */ 
#define PDC_RXTDIS      ((unsigned int) 0x1 <<  1) /* (PDC) Receiver Transfer Disable    */ 
#define PDC_TXTEN       ((unsigned int) 0x1 <<  8) /* (PDC) Transmitter Transfer Enable  */ 
#define PDC_TXTDIS      ((unsigned int) 0x1 <<  9) /* (PDC) Transmitter Transfer Disable */ 


/* *****************************************************************************
 * System Peripheral Interface (SPI)
 * *****************************************************************************/
#define SPI_BASE	AT91C_BASE_SPI
#define SPI_REG(x)	*(volatile UINT32 *)(SPI_BASE + (x))

/* Register Offsets */
#define SPI_CR    0x00 /* (SPI) Control Register           */
#define SPI_MR    0x04 /* (SPI) Mode Register              */
#define SPI_RDR   0x08 /* (SPI) Receive Data Register      */
#define SPI_TDR   0x0C /* (SPI) Transmit Data Register     */
#define SPI_SR    0x10 /* (SPI) Status Register            */
#define SPI_IER   0x14 /* (SPI) Interrupt Enable Register  */
#define SPI_IDR   0x18 /* (SPI) Interrupt Disable Register */
#define SPI_IMR   0x1C /* (SPI) Interrupt Mask Register    */
#define SPI_CSR   0x30 /* (SPI) Chip Select Register       */

/* *****************************************************************************
 * Two Wire Interface (TWI)
 * *****************************************************************************/
#define TWI_BASE	AT91C_BASE_TWI
#define TWI_REG(x)	*(volatile UINT32 *)(TWI_BASE + (x))

/* Register Offsets */
#define TWI_RHR   0x30 /* (TWI) Receive Holding Register            */ 
#define TWI_IDR   0x28 /* (TWI) Interrupt Disable Register          */ 
#define TWI_SR    0x20 /* (TWI) Status Register                     */ 
#define TWI_CWGR  0x10 /* (TWI) Clock Waveform Generator Register   */ 
#define TWI_SMR   0x08 /* (TWI) Slave Mode Register                 */ 
#define TWI_CR    0x00 /* (TWI) Control Register                    */ 
#define TWI_THR   0x34 /* (TWI) Transmit Holding Register           */ 
#define TWI_IMR   0x2C /* (TWI) Interrupt Mask Register             */ 
#define TWI_IER   0x24 /* (TWI) Interrupt Enable Register           */ 
#define TWI_IADR  0x0C /* (TWI) Internal Address Register            */
#define TWI_MMR   0x04 /* (TWI) Master Mode Register                */