byte_crc.tan.summary

字节型CRC校验 采用verilog语言设计

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.984 ns
From           : pdata[6]
To             : buf_crc[14]
From Clock     : --
To Clock       : sig
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.831 ns
From           : buf_crc[7]
To             : crc[7]
From Clock     : sig
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.675 ns
From           : pdata[5]
To             : buf_crc[1]
From Clock     : --
To Clock       : sig
Failed Paths   : 0

Type           : Clock Setup: 'sig'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 340.02 MHz ( period = 2.941 ns )
From           : buf_crc[7]
To             : buf_crc[15]
From Clock     : sig
To Clock       : sig
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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