📄 cncodec.c
字号:
break;
case 3:
Timeon_low=0xe0;
Timeon_high=0x15;
Timeoff_low=0xe0;
Timeoff_high=0x15;
Freq=0x7e00;
Gain=0x32;
Phase=0x0;
Control=0x3e;
break;
default:
break;
}
WriteDrProSLIC(codec_cs,36, Timeon_low); //time on
WriteDrProSLIC(codec_cs,37, Timeon_high); // time on
WriteDrProSLIC(codec_cs, 38, Timeoff_low); // time off
WriteDrProSLIC(codec_cs,39, Timeoff_high); // time off
WriteInDrProSLIC(codec_cs, 0, Freq); //frequency 450HZ
WriteInDrProSLIC(codec_cs, 1, Gain); //gain control
WriteInDrProSLIC(codec_cs, 2, Phase);
WriteDrProSLIC(codec_cs, 32, Control);
}
//########################################################
//the following programs are added for 3050(true fxo scheme)
/******************************************
unsigned short Read_cpld_3050(void)
read data from codec spi via cpld
*******************************************/
unsigned short Read_cpld_3050(void)
{
unsigned short i,data=0,data1;
unsigned short j=0,delay=1000;
CPLD_WRITE_DATA(CS_3050,0); /*set cs*/
for(j=0; j<delay;j++);
for(i=8;i>0;i--)
{
CPLD_WRITE_DATA(CLK_PROSLIC,0); /*set clk*/
for(j=0; j<delay;j++);
CPLD_READ_DATA(READ_PROSLIC,data1);
data1 = data1&0x01;
data |= data1<<(i-1);
for(j=0; j<delay;j++);
CPLD_WRITE_DATA(CLK_PROSLIC,1); /*set clk*/
for(j=0; j<delay;j++);
}
CPLD_WRITE_DATA(CS_3050,1); /*set cs*/
for(j=0; j<delay;j++);
return data;
}
/******************************************
void Write_cpld_3050(unsigned short data)
write data to codec spi via cpld
*******************************************/
void Write_cpld_3050(unsigned short data)
{
unsigned short i,data1;
unsigned short j=0,delay=1000;
CPLD_WRITE_DATA(CS_3050,0); /*set cs*/
for(j=0; j<delay;j++);
for(i=8;i>0;i--)
{
data1 = data >>(i-1);
data1 = data1 & 1;
CPLD_WRITE_DATA(WRITE_PROSLIC,data1); /*write bit*/
for(j=0; j<delay;j++);
CPLD_WRITE_DATA(CLK_PROSLIC,0); /*set clk*/
for(j=0; j<delay;j++);
CPLD_WRITE_DATA(CLK_PROSLIC,1); /*set clk*/
for(j=0; j<delay;j++);
}
CPLD_WRITE_DATA(CS_3050,1); /*set cs*/
for(j=0; j<delay;j++);
}
/*****************************************
UINT8 ReadDr3050(UINT8 addr)
rear data from the 3050 direct register
*****************************************/
UINT8 ReadDr3050(UINT8 addr)
{
UINT8 data;
Write_cpld_3050(0x60); //write control byte,choose the firs 3050
Write_cpld_3050(addr); //write address byte
data = Read_cpld_3050();
cpld_rw_sync(1);
return data;
}
/*****************************************
void WriteDr3050(UINT8 addr,UINT8 data)
write data to the 3050 direct register
*****************************************/
void WriteDr3050(UINT8 addr,UINT8 data)
{
Write_cpld_3050(0x20); //write control byte,choose the firs 3050
Write_cpld_3050(addr);
Write_cpld_3050(data);
}
int init3050(void)
{
UINT8 i;
/*reset the Proslic*/
CPLD_WRITE_DATA(REST_3050,0);
for(i=0;i<18;i++)
cpld_rw_sync(1);
CPLD_WRITE_DATA(CS_3050,1);
CPLD_WRITE_DATA(CLK_PROSLIC,1);
cpld_rw_sync(1);
CPLD_WRITE_DATA(REST_3050,1);
for(i=0;i<18;i++)
cpld_rw_sync(1);
if (ReadDr3050(2) !=3||ReadDr3050(6) !=0x10||ReadDr3050(22) !=0x96)
{
CODEC_ASSERT(0);
return SI3050_ERROR;
}
WriteDr3050( 33,DR33_3050); //
WriteDr3050( 26,DR26_3050); //
WriteDr3050( 30,DR30_3050); //
WriteDr3050( 16,DR16_3050); //
WriteDr3050( 17,DR17_3050); //
WriteDr3050( 18,DR18_3050); //
WriteDr3050( 22,DR22_3050); //
WriteDr3050( 23,DR23_3050); //
WriteDr3050( 24,DR24_3050); //
WriteDr3050( 31,DR31_3050); //
WriteDr3050( 34,DR34_3050); //
WriteDr3050( 36,DR36_3050); //
WriteDr3050( 38,DR38_3050); //
WriteDr3050( 39,DR39_3050); //
WriteDr3050( 40,DR40_3050); //
WriteDr3050( 41,DR41_3050); //
WriteDr3050( 6,DR6_3050); //
WriteDr3050( 5,DR5_3050); //
#if CODEC_DEBUG
printk( "\nSI3050 initializing OK\n");
#endif
return SI3050_OK;
}
UINT8 fxo_connection_status(int chan) //detect whether the FXO has been connected
{
UINT8 data;
//if data==0,fxo has not been connected ;
//if data changed between negative and positive,the fxo has occured a Polarity reversal.
data=ReadDr3050(29);
return data;
}
void CID_enable(int chan, UINT8 i) //enable CID mode,i=0,disable; i=1,enable
{
if(i==0)
WriteDr3050(5, 0x00);
if(i==1)
WriteDr3050(5, 0x08);
}
void PCM_enable(int chan,UINT8 i) //i=1,enable PCM,this is default mode; i=0,disable PCM
{ short m=0;
m=ReadDrProSLIC(chan,2);
if(i==0)
WriteDrProSLIC(chan,2,m+128);
if(i==1)
WriteDrProSLIC(chan,2,m-128);
}
/*
Set or Read : Analog Transmit Path Gain. and Analog Receive Path Gain.
0 0dB
-1 -3.5dB
1 +3.5dB
*/
void ova_si3215_set(int chan,int i) // Set Analog Transmit Path Gain.
{
UINT8 m;
m=ReadDrProSLIC(chan,9);
switch(i){
case 0: WriteDrProSLIC(chan,9, (UINT8)(m&0xf3));
break;
case 1: WriteDrProSLIC(chan,9, (UINT8)((m&0xf3)|0x8));
break;
case -1: WriteDrProSLIC(chan,9, (UINT8)((m&0xf3)|0x4));
break;
default:
printk("ERROR: input ' i ' must be 0 -1 or 1,other value is inefficacy!!!");
break;
}
}
int ova_si3215_read(int chan) // Read Analog Transmit Path Gain.
{
UINT8 m=0; int n=0;
m=(ReadDrProSLIC(chan,9)&0xc)>>2;
switch(m){
case 0: n=0;
break;
case 1: n=-1;
break;
case 2: n=1;
break;
default:
break;
}
return n;
}
void iva_si3215_set(int chan,int i) // Set Analog Receive Path Gain.
{
UINT8 m;
m=ReadDrProSLIC(chan,9);
switch(i){
case 0: WriteDrProSLIC(chan,9,m&0xfc);
break;
case 1: WriteDrProSLIC(chan,9,(m&0xfc)|0x2);
break;
case -1: WriteDrProSLIC(chan,9,(m&0xfc)|0x1);
break;
default:
printk("ERROR: input ' i ' must be 0 -1 or 1,other value is inefficacy!!!");
break;
}
}
int iva_si3215_read(int chan) // Read Analog Receive Path Gain.
{
UINT8 m=0;
int n=0;
m=ReadDrProSLIC(chan,9)&0x3;
switch(m){
case 0: n=0;
break;
case 1: n=-1;
break;
case 2: n=1;
break;
default:
break;
}
return n;
}
/*Set or Read :Receive/Transmit Path Digital to Analog Converter Gain/Attenuation
i dB
20 6dB
0 0dB
-20 mute
*/
void ivd_si3215_set(int chan,int i) //Set Receive Path Digital to Analog Converter Gain/Attenuation.
{
int m=0;
UINT16 n=0;
m=1024+i*44;
n=(UINT16)m;
WriteInDrProSLIC(chan,26,n<<4);
}
int ivd_si3215_read(int chan) //Read Receive Path Digital to Analog Converter Gain/Attenuation.
{
int m=0;
UINT16 n=0;
n=ReadInDrProSLIC(chan,26)>>4;
m=(n-1024)/44;
return m;
}
void ovd_si3215_set(int chan,int i) //Set Transmit Path Analog to Digital Converter Gain/Attenuation.
{
int m=0;
UINT16 n=0;
m=1024+i*44;
n=(UINT16)m;
WriteInDrProSLIC(chan,27,n<<4);
}
int ovd_si3215_read(int chan) //Read Transmit Path Analog to Digital Converter Gain/Attenuation.
{
int m=0;
UINT16 n=0;
n=ReadInDrProSLIC(chan,27)>>4;
m=(n-1024)/44;
return m;
}
/*
set the Two_wire_impedance.
bit2 bit1 bit0 i resut
000 0 =600 Ω
001 1 = 900 Ω
010 2 = Japan (600 Ω + 1 μF); requires external resistor RZREF = 12 kΩ and C3, C4 = 100 nF.
011 3 = 900 Ω + 2.16 μF; requires external resistor RZREF = 18 kΩ and C3, C4 = 220 nF.
100 4 = CTR21 270 Ω + (750 Ω || 150 nF)
101 5 = Australia/New Zealand 220 Ω + (820 Ω || 120 nF)
110 6 = Slovakia/Slovenia/South Africa 220 Ω + (820 Ω || 115 nF)
111 7 = China voice apply 200 Ω + (680 Ω || 100 nF)
*/
void Set_Two_wire_impedance_control(int chan,UINT8 i) //set the Two_wire_impedance.
{
WriteDrProSLIC(chan,10,(i&0x7)|0x28);
}
UINT8 Get_Two_wire_impedance_control(int chan) //Read the Two_wire_impedance.
{
return ReadDrProSLIC(chan,10)&0x7;
}
/*
FXO si3050 Country Specific Register Settings.Include On-Hook Speed;TIP/RING Voltage Adjust;AC Impedance.
Default country_code is 0.
country_code country
1 Argentina,Brazil,Canada,Chile,China(include Taiwan ,Hong Kong, Macao,),
Colombia,Ecuador,El Salvador,Guam,India,Indonesia,Kazakhstan,Mexico,
Peru,Russia,Saudi Arabia,Singapore,USA,Yemen
2 Australia
3 Austria,Bahrain,Belgium,Croatia,Cyprus,Czech Republic,Denmark,Egypt,
Finland,France,Germany,Greece,Hungary,Iceland,Ireland,Israel,Italy,Latvia,
Lebanon,Luxembourg,Malta,Morocco,Netherlands,Nigeria,Norway,Poland,Portugal,
Romania,Slovakia,Slovenia,Spain,Sweden,Switzerland
4 Bulgaria
5 Japan,Jordan,Malaysia,Oman,Pakistan,Philippines,Thailand
6 New Zealand
7 South Africa
8 South Korea
9 United Kingdom
10 TBR21
*/
void Si3050_Country_Set(UINT8 country_code)
{
UINT8 i=0,si3050_dr16=0,si3050_dr26=0,si3050_dr30=0,si3050_dr31=0;
i=country_code;
switch(i)
{
case 0: si3050_dr16=0x10; si3050_dr26=0xc0; si3050_dr30=0x00; si3050_dr31=0xa0;
break;
case 1: si3050_dr16=0x50; si3050_dr26=0x50; si3050_dr30=0x03; si3050_dr31=0xa0;
break;
case 2: si3050_dr16=0x10; si3050_dr26=0xc2; si3050_dr30=0x02; si3050_dr31=0xa8;
break;
case 3: si3050_dr16=0x10; si3050_dr26=0xc2; si3050_dr30=0x03; si3050_dr31=0xa8;
break;
case 4: si3050_dr16=0x10; si3050_dr26=0x50; si3050_dr30=0x00; si3050_dr31=0xa0;
break;
case 5: si3050_dr16=0x10; si3050_dr26=0xc0; si3050_dr30=0x04; si3050_dr31=0xa0;
break;
case 6: si3050_dr16=0x12; si3050_dr26=0xc0; si3050_dr30=0x03; si3050_dr31=0xa0;
break;
case 7: si3050_dr16=0x12; si3050_dr26=0xc0; si3050_dr30=0x00; si3050_dr31=0xa0;
break;
case 8: si3050_dr16=0x10; si3050_dr26=0xc2; si3050_dr30=0x05; si3050_dr31=0xa8;
break;
case 9: si3050_dr16=0x10; si3050_dr26=0xc2; si3050_dr30=0x02; si3050_dr31=0xa0;
break;
default:
printk("Error:%s %d Si3050_Country_Set() country_code %d\n\r",__FILE__, __LINE__, country_code);
break;
}
WriteDr3050(16,si3050_dr16);
WriteDr3050(26,si3050_dr26);
WriteDr3050(30,si3050_dr30);
WriteDr3050(31,si3050_dr31);
}
/* FXO si3050 Receive Gain read . unit dB*/
int iv_si3050_read(void)
{
int m,gain;
m=ReadDr3050(39);
gain=(m>15)?(16-m):m;
return gain;
}
/* FXO si3050 Receive Gain set . -15=<gain<=12 unit dB*/
void iv_si3050_set(int gain)
{
int m;
m=(gain>0)?gain:(-1*gain)|0x10;
WriteDr3050(39,m);
}
/* FXO si3050 Transmit Gain read .unit dB*/
int ov_si3050_read(void)
{
int m,gain;
m=ReadDr3050(38);
gain=(m>15)?(16-m):m;
return gain;
}
/* FXO si3050 Transmit Gain set . -15=<gain<=12 unit dB*/
void ov_si3050_set(int gain)
{
int m;
m=(gain>0)?gain:(-1*gain)|0x10;
WriteDr3050(39,m);
}
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