📄 cncodec.h
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#ifndef __INCLUDE_CODEC_H_
#define __INCLUDE_CODEC_H_
#include "common.h"
/**/
#define INIT_IR0 0x55C2 // DTMF_ROW_0_PEAK
#define INIT_IR1 0x51E6 // DTMF_ROW_0_PEAK,
#define INIT_IR2 0x4B85 // DTMF_ROW_1_PEAK,
#define INIT_IR3 0x4937 // DTMF_ROW2_PEAK,
#define INIT_IR4 0x3333 // DTMF_ROW3_PEAK,
#define INIT_IR5 0x0202 // DTMF_COL1_PEAK,
#define INIT_IR6 0x0202 // DTMF_FWD_TWIST,
#define INIT_IR7 0x0198 // DTMF_RVS_TWIST,
#define INIT_IR8 0x0198 // DTMF_ROW_RATIO,
#define INIT_IR9 0x0611 // DTMF_COL_RATIO,
#define INIT_IR10 0x0202 // DTMF_ROW_2ND_ARM,
#define INIT_IR11 0x00E5 // DTMF_COL_2ND_ARM,
#define INIT_IR12 0x0A1C // DTMF_PWR_MIN_,
#define INIT_IR13 0x7b30 // DTMF_OT_LIM_TRES,
#define INIT_IR14 0x0063 // OSC1_COEF,
#define INIT_IR15 0x0000 // OSC1X,
#define INIT_IR16 0x7870 // OSC1Y,
#define INIT_IR17 0x007d // OSC2_COEF,
#define INIT_IR18 0x0000 // OSC2X,
#define INIT_IR19 0x0000 // ringing dc offset 0V
#define INIT_IR20 0x7E6C // Ringing Oscillator Frequency Coefficient. 25HZ
#define INIT_IR21 0x023A // Ringing Oscillator Amplitude Register. 85V
#define INIT_IR22 0x0000 // RING_X,
#define INIT_IR23 0x2000 // RING_Y,
#define INIT_IR24 0x2000 // PULSE_ENVEL,
#define INIT_IR25 0x0000 // PULSE_X,
#define INIT_IR26 0x4000 // PULSE_Y,
#define INIT_IR27 0x4000 // RECV_DIGITAL_GAIN,
#define INIT_IR28 0x1600 // //11*1.27=13.97mA edit by gaofc
#define INIT_IR29 0x3600 // LOOP_CLOSE_TRES,
#define INIT_IR30 0x1000 // RING_TRIP_TRES,
#define INIT_IR31 0x0080 //0x0200 // COMMON_MIN_TRES,
#define INIT_IR32 0x17c0 //0x37c0 // COMMON_MAX_TRES,
#define INIT_IR33 0x376f //0x5600 // PWR_ALARM_Q1Q2,
#define INIT_IR34 0x1b80 //0x2B80 // PWR_ALARM_Q3Q4,
#define INIT_IR35 0x8000 // PWR_ALARM_Q5Q6,
#define INIT_IR36 0x0350 // LOOP_CLSRE_FlTER,
#define INIT_IR37 0x08c // RING_TRIP_FILTER,
#define INIT_IR38 0x0100 // TERM_LP_POLE_Q1Q2,
#define INIT_IR39 0x010 // TERM_LP_POLE_Q3Q4,
#define INIT_IR40 0x0600 // TERM_LP_POLE_Q5Q6, ///////////////0x00
#define INIT_IR41 0x0600 // CM_BIAS_RINGING,
#define INIT_IR42 0x1000 // DCDC_MIN_V,
#define INIT_IR43 0x1400 //0x00DA // "LOOP_CLOSE_TRES Low
#define INIT_IR99 0x00DA // FSK 0 FREQ PARAM
#define INIT_IR100 0x6B60 // FSK 0 AMPL PARAM
#define INIT_IR101 0x0074 // FSK 1 FREQ PARAM
#define INIT_IR102 0x79C0 // FSK 1 AMPl PARAM
#define INIT_IR103 0x1120 // FSK 0to1 SCALER
#define INIT_IR104 0x3BE0 // FSK 1to0 SCALER
#define INIT_IR97 0x0000 // TRASMIT_FILTER
/**/
#define INIT_DR0 0X00 // Serial Interface
#ifdef CODEC_A_LAW
#define INIT_DR1 0X21 // PCM A LawMode
#else
//#define INIT_DR1 0X29 // PCM Mu Law Mode
#define INIT_DR1 0X3c // NO G.711 mode,3c changed to 3d by liubing on Nov 7,06
#endif
#define INIT_DR2 0X01 // PCM TX Clock Slot Low Byte (1 PCLK cycle/LSB)
#define INIT_DR3 0x00 // PCM TX Clock Slot High Byte
#define INIT_DR4 0x01 // PCM RX Clock Slot Low Byte (1 PCLK cycle/LSB)
#define INIT_DR5 0x00 // PCM RX Clock Slot High Byte
#define INIT_DR6 0x00 // DIO Control (external battery operation, Si3211/12)
#define INIT_DR8 0X00 // Loopbacks (digital loopback default)
#define INIT_DR9 0x00 // Transmit and receive path gain and control
#define INIT_DR10 0X28 // Initialization Two-wire impedance (600 and enabled)
#define INIT_DR11 0x33 // Transhybrid Balance/Four-wire Return Loss
#define INIT_DR14 0X10 // Powerdown Control 1
#define INIT_DR15 0x00 // Initialization Powerdown Control 2
#define INIT_DR18 0xff // Normal Oper. Interrupt Register 1 (clear with 0xFF)
#define INIT_DR19 0xff // Normal Oper. Interrupt Register 2 (clear with 0xFF)
#define INIT_DR20 0xff // Normal Oper. Interrupt Register 3 (clear with 0xFF)
#define INIT_DR21 0xff /**/// Interrupt Mask 1
#define INIT_DR22 0xff /**/// Initialization Interrupt Mask 2
#define INIT_DR23 0xff /**/// Initialization Interrupt Mask 3
#define INIT_DR32 0x00 // Oper. Oscillator 1 Controltone generation
#define INIT_DR33 0x00 // Oper. Oscillator 2 Controltone generation
#define INIT_DR34 0X18 // 34 0x22 0x00 Initialization Ringing Oscillator Control,ringing no dc offset enable
#define INIT_DR35 0x00 // Oper. Pulse Metering Oscillator Control
#define INIT_DR36 0x00 // 36 0x24 0x00 Initialization OSC1 Active Low Byte (125 µs/LSB)
#define INIT_DR37 0x00 // 37 0x25 0x00 Initialization OSC1 Active High Byte (125 µs/LSB)
#define INIT_DR38 0x00 // 38 0x26 0x00 Initialization OSC1 Inactive Low Byte (125 µs/LSB)
#define INIT_DR39 0x00 // 39 0x27 0x00 Initialization OSC1 Inactive High Byte (125 µs/LSB)
#define INIT_DR40 0x00 // 40 0x28 0x00 Initialization OSC2 Active Low Byte (125 µs/LSB)
#define INIT_DR41 0x00 // 41 0x29 0x00 Initialization OSC2 Active High Byte (125 µs/LSB)
#define INIT_DR42 0x00 // 42 0x2A 0x00 Initialization OSC2 Inactive Low Byte (125 µs/LSB)
#define INIT_DR43 0x00 // 43 0x2B 0x00 Initialization OSC2 Inactive High Byte (125 µs/LSB)
#define INIT_DR44 0x00 // 44 0x2C 0x00 Initialization Pulse Metering Active Low Byte (125 µs/LSB)
#define INIT_DR45 0x00 // 45 0x2D 0x00 Initialization Pulse Metering Active High Byte (125 µs/LSB)
#define INIT_DR46 0x00 // 46 0x2E 0x00 Initialization Pulse Metering Inactive Low Byte (125 µs/LSB)
#define INIT_DR47 0x00 // 47 0x2F 0x00 Initialization Pulse Metering Inactive High Byte (125 µs/LSB)
#define INIT_DR48 0X80 // 48 0x30 0x00 0x80 Initialization Ringing Osc. Active Timer Low Byte (2 s,125 µs/LSB)
#define INIT_DR49 0X3E // 49 0x31 0x00 0x3E Initialization Ringing Osc. Active Timer High Byte (2 s,125 µs/LSB)
#define INIT_DR50 0X00 // 50 0x32 0x00 0x00 Initialization Ringing Osc. Inactive Timer Low Byte (4 s, 125 µs/LSB)
#define INIT_DR51 0X7D // 51 0x33 0x00 0x7D Initialization Ringing Osc. Inactive Timer High Byte (4 s, 125 µs/LSB)
#define INIT_DR52 0X00 // 52 0x34 0x00 Normal Oper. FSK Data Bit
#define INIT_DR63 0X54 // 63 0x3F 0x54 Initialization Ringing Mode Loop Closure Debounce Interval
#define INIT_DR64 0x01 // 64 0x40 0x00 Normal Oper. Mode Byteprimary control
#define INIT_DR65 0X61 // 65 0x41 0x61 Initialization External Bipolar Transistor Settings
#define INIT_DR66 0X03 // 66 0x42 0x03 Initialization Battery Control
#define INIT_DR67 0X16 // 67 0x43 0x1F Initialization Automatic/Manual Control
#define INIT_DR69 0X28 // //0x0c 69 0x45 0x0A 0x0C Initialization Loop Closure Debounce
#define INIT_DR70 0X0A // 70 0x46 0x0A Initialization Ring Trip Debounce Interval (1.25 ms/LSB)
#define INIT_DR71 0X01 // //0x01 edit by gaofc 71 0x47 0x00 0x01 Initialization Off-Hook
#define INIT_DR72 0X20 // 72 0x48 0x20 Initialization On-Hook Voltage (open circuit voltage) = 48 V(1.5 V/LSB)
#define INIT_DR73 0X02 // 73 0x49 0x02 Initialization Common Mode VoltageVCM = ? V(?.5 V/LSB)
#define INIT_DR74 0X38 // VBATH=85 V
#define INIT_DR75 0X0C // VBATL=-18 V TRACK=1 姝よ缃病鐢?
#define INIT_DR92 0xff // 92 0x5C 7F Initialization DCDC Converter PWM Period (61.035 ns/LSB)
#define INIT_DR93 0x18 // 93 0x5D 0x14 0x19 Initialization DCDC Converter Min. Off Time (61.035 ns/LSB)
#define INIT_DR96 0x00 // 96 0x60 0x1F Initialization Calibration Control Register 1(written second and starts calibration)
#define INIT_DR97 0X1F // 97 0x61 0x1F Initialization Calibration Control Register 2(written before Register 96)
#define INIT_DR98 0X10 // 98 0x62 0x10 Informative Calibration result (see data sheet)
#define INIT_DR99 0X10 // 99 0x63 0x10 Informative Calibration result (see data sheet)
#define INIT_DR100 0X11 // 100 0x64 0x11 Informative Calibration result (see data sheet)
#define INIT_DR101 0X11 // 101 0x65 0x11 Informative Calibration result (see data sheet)
#define INIT_DR102 0x08 // 102 0x66 0x08 Informative Calibration result (see data sheet)
#define INIT_DR103 0x88 // 103 0x67 0x88 Informative Calibration result (see data sheet)
#define INIT_DR104 0x00 // 104 0x68 0x00 Informative Calibration result (see data sheet)
#define INIT_DR105 0x00 // 105 0x69 0x00 Informative Calibration result (see data sheet)
#define INIT_DR106 0x20 // 106 0x6A 0x20 Informative Calibration result (see data sheet)
#define INIT_DR107 0x08 // 107 0x6B 0x08 Informative Calibration result (see data sheet)
#define INIT_DR108 0xeb //0xEB // 108 0x63 0x00 0xEB Initialization Feature enhancement register
#define INIT_SI3210M_DR92 0xc1/**/ // 92 0x60 Initialization DCDC Converter PWM Period (61.035 ns/LSB)
#define INIT_SI3210M_DR93 0x38 /**/// 92 0x60 Initialization DCDC Converter PWM Period (61.035 ns/LSB)
#define IDA_LO 28/**/
#define IDA_HI 29/**/
#define IAA 30/**/
#define I_STATUS 31/**/
#define BIT_CALCM_DR97 0x01 /**/// CALCM Common Mode Balance Calibration.
#define CAL_COMPLETE_DR96 0 /**/// Value in dr96 after calibration is completed
#define MAX_CAL_PERIOD 800 /**/// The longest period in ms. for a calibration to complete.
#define OPEN_DR64 0 /**/
#define ENB2_DR23 1<<2 /**/// enable interrupt for the balance Cal
#define DISABLE_ALL_DR21 0/**/
#define DISABLE_ALL_DR22 0/**/
#define DISABLE_ALL_DR23 0/**/
/////////////////////////////////////////////
#define CPLD_WRITE_DATA(addr,data) *(unsigned short *)addr = data
#define CPLD_READ_DATA(addr,data) data = *(unsigned short *)addr
#define CLK_PROSLIC 0x20200080
#define CS_PROSLIC 0x20200090
#define WRITE_PROSLIC 0x202000A0
#define REST_PROSLIC 0x202000B0
#define READ_PROSLIC 0x20200000
#define CS_3050 0x202000C0 //ADD FOR 3050
#define REST_3050 0x202000D0 //ADD FOR 3050
void set_led(int chan, unsigned char status);
void set_trunk(unsigned char chan,unsigned char opcode);
unsigned char get_line_type(unsigned char chan);
unsigned char ReadType(unsigned int addr);
int initProSLIC(UINT8 codec_cs);
void SetSlic(int ch,int opcode);
UINT8 ReadDrProSLIC(UINT8 codec_cs,UINT8 addr);
void WriteDrProSLIC(UINT8 codec_cs,UINT8 addr,UINT8 data);
void WriteInDrProSLIC(UINT8 codec_cs,UINT8 addr,UINT16 data);
UINT16 ReadInDrProSLIC(UINT8 codec_cs,UINT8 addr);
int Si3215orSi3216(UINT8 codec_cs);
UINT8 possibleAddressCorrect(UINT8 codec_cs,UINT8 address);
//UINT8 RReadDrProSLIC(UINT8 addr);
int verifyIndirectReg(UINT8 codec_cs,UINT8 addr, UINT16 should_be_value);
int verifyIndirectRegisters(UINT8 codec_cs,UINT8 familycodec) ;
int calibrate(UINT8 codec_cs);
UINT8 powerUp(UINT8 codec_cs);
unsigned short Read_cpld(void);
void Write_cpld(unsigned short data);
void ADSP_tone(UINT8 codec_cs,int tone_type );
unsigned short Read_cpld_3050(void);
void Write_cpld_3050(unsigned short data);
UINT8 ReadDr3050(UINT8 addr);
void WriteDr3050(UINT8 addr,UINT8 data);
int init3050(void);
void oh3050(UINT8 status) ;
UINT8 fxo_connection_status(int chan);
void CID_enable(int chan, UINT8 i);
void PCM_enable(int chan,UINT8 i) ;
void ova_si3215_set(int chan, int i);
void iva_si3215_set(int chan,int i);
void Si3050_Country_Set(UINT8 country_code);
#define DR16_3050 0x10 //dr16 dr17 china standerer:10,00,16v5
#define DR17_3050 0x00 //11,10 49.5v
#define DR18_3050 0x02 //02 full wave 00 half wave
#define DR5_3050 0x00 //
#define DR6_3050 0x00 //
#define DR22_3050 0x4b //
#define DR23_3050 0x09 //
#define DR24_3050 0x91 //
#define DR26_3050 0xc2 //china mode,add full/full2 scale must put,dcv[1:0]=11,data[7:6],mini[1:0]=00,data[5:4] Current Limiting Enable
#define DR30_3050 0x0a //china mode,data4=1,FULL 2X T/R enable
#define DR31_3050 0xa0 //data7=1,full enable
#define DR33_3050 0x38 //Enable PCM mode 20h ALaw, 28h uLaw,38h 16-bit Linear
#define DR34_3050 0x11 //PCM transmit from bit 17 to 32
#define DR36_3050 0x11 //PCM receive from bit 17 to 32
#define DR38_3050 0x03 //TX gain 3 dB
#define DR39_3050 0x03 //RX gain 3 dB
#define DR40_3050 0x00 //TX gain 0 dB
#define DR41_3050 0x00 //RX gain 0dB
#define CODEC_ASSERT(p) (p)?(void)0:printk("ASSERT in file %s:%d\r\n", __FILE__, __LINE__)
#define CODEC_DEBUG 0
#endif
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