sw_two.tan.qmsg

项目程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 29 12:12:52 2008 " "Info: Processing started: Sat Mar 29 12:12:52 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sw_two -c sw_two " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sw_two -c sw_two" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[0\] c 10.000 ns Longest " "Info: Longest tpd from source pin \"a\[0\]\" to destination pin \"c\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns a\[0\] 1 PIN PIN_1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_1; Fanout = 1; PIN Node = 'a\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sw_two" "UNKNOWN" "V1" "C:/altera/quartus51/mydesign/syn_test/sw_two/db/sw_two.quartus_db" { Floorplan "C:/altera/quartus51/mydesign/syn_test/sw_two/" "" "" { a[0] } "NODE_NAME" } "" } } { "sw_two.vhd" "" { Text "C:/altera/quartus51/mydesign/syn_test/sw_two/sw_two.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(4.400 ns) 8.400 ns c~1 2 COMB LC80 1 " "Info: 2: + IC(2.600 ns) + CELL(4.400 ns) = 8.400 ns; Loc. = LC80; Fanout = 1; COMB Node = 'c~1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sw_two" "UNKNOWN" "V1" "C:/altera/quartus51/mydesign/syn_test/sw_two/db/sw_two.quartus_db" { Floorplan "C:/altera/quartus51/mydesign/syn_test/sw_two/" "" "7.000 ns" { a[0] c~1 } "NODE_NAME" } "" } } { "sw_two.vhd" "" { Text "C:/altera/quartus51/mydesign/syn_test/sw_two/sw_two.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 10.000 ns c 3 PIN PIN_50 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.000 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'c'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sw_two" "UNKNOWN" "V1" "C:/altera/quartus51/mydesign/syn_test/sw_two/db/sw_two.quartus_db" { Floorplan "C:/altera/quartus51/mydesign/syn_test/sw_two/" "" "1.600 ns" { c~1 c } "NODE_NAME" } "" } } { "sw_two.vhd" "" { Text "C:/altera/quartus51/mydesign/syn_test/sw_two/sw_two.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 74.00 % ) " "Info: Total cell delay = 7.400 ns ( 74.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 26.00 % ) " "Info: Total interconnect delay = 2.600 ns ( 26.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sw_two" "UNKNOWN" "V1" "C:/altera/quartus51/mydesign/syn_test/sw_two/db/sw_two.quartus_db" { Floorplan "C:/altera/quartus51/mydesign/syn_test/sw_two/" "" "10.000 ns" { a[0] c~1 c } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { a[0] a[0]~out c~1 c } { 0.000ns 0.000ns 2.600ns 0.000ns } { 0.000ns 1.400ns 4.400ns 1.600ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 29 12:12:52 2008 " "Info: Processing ended: Sat Mar 29 12:12:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}