clkspeedup.vhd

NAND FLASH 读写控制以及ECC的VHDL源程序

-- Module clkSPEEDup
-- Generated by Xilinx Architecture Wizard
-- VHDL
-- Written for synthesis tool: XST

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- synopsys translate_off
Library UNISIM;
use UNISIM.Vcomponents.all;
-- synopsys translate_on

entity clkSPEEDup is
    port (
        RST_IN : in std_logic;
        CLKIN_IN : in std_logic;
        LOCKED_OUT : out std_logic;
        CLK2X_OUT : out std_logic;
        CLKDV_OUT : out std_logic;
        CLKIN_IBUFG_OUT : out std_logic;
        CLK0_OUT : out std_logic);
end clkSPEEDup;

architecture STRUCT of clkSPEEDup is
   signal CLKIN_IBUFG : std_logic;
   signal CLKFB_IN : std_logic;
   signal CLK0_BUF : std_logic;
   signal CLKDV_BUF : std_logic;
   signal CLK2X_BUF : std_logic;
   signal GND : std_logic;


   component DCM
    generic( 
       CLKDV_DIVIDE : real := 2.0;
       CLKFX_DIVIDE : integer := 1;
       CLKFX_MULTIPLY : integer := 4;
       CLKIN_DIVIDE_BY_2 : boolean := false;
       CLKIN_PERIOD : real := 0.0;                         
       CLKOUT_PHASE_SHIFT : string := "NONE";
       CLK_FEEDBACK : string := "1X";
       DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";     
       DFS_FREQUENCY_MODE : string := "LOW";
       DLL_FREQUENCY_MODE : string := "LOW";
       DSS_MODE : string := "NONE";                        
       DUTY_CYCLE_CORRECTION : boolean := true;
       FACTORY_JF : bit_vector := X"C080";                 
       MAXPERCLKIN : time := 1000000 ps;                   
       MAXPERPSCLK : time := 100000000 ps;                 
       PHASE_SHIFT : integer := 0;
       SIM_CLKIN_CYCLE_JITTER : time := 300 ps;            
       SIM_CLKIN_PERIOD_JITTER : time := 1000 ps;          
       STARTUP_WAIT : boolean := false                     
     );
     port (
       CLKIN : in std_logic;
       CLKFB : in std_logic;
       RST : in std_logic;
       PSEN : in std_logic;
       PSINCDEC : in std_logic;
       PSCLK : in std_logic;
       DSSEN : in std_logic;
       CLK0 : out std_logic;
       CLK90 : out std_logic;
       CLK180 : out std_logic;
       CLK270 : out std_logic;
       CLKDV : out std_logic;
       CLK2X : out std_logic;
       CLK2X180 : out std_logic;
       CLKFX : out std_logic;
       CLKFX180 : out std_logic;
       STATUS : out std_logic_vector (7 downto 0);
       LOCKED : out std_logic;
       PSDONE : out std_logic
       );
   end component;
   component IBUFG
     port (
       I : in std_logic;
       O : out std_logic
       );
   end component;
   component BUFG
     port (
       I : in std_logic;
       O : out std_logic
       );
   end component;

begin
   DCM_INST : DCM
    Generic map (
      CLK_FEEDBACK => "1X",
      CLKDV_DIVIDE => 1.5,
      CLKFX_DIVIDE => 1,
      CLKFX_MULTIPLY => 4,
      CLKIN_DIVIDE_BY_2 => FALSE,
      CLKIN_PERIOD => 20.0,
      CLKOUT_PHASE_SHIFT => "NONE",
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
      DFS_FREQUENCY_MODE => "LOW",
      DLL_FREQUENCY_MODE => "LOW",
      DUTY_CYCLE_CORRECTION => TRUE,
      PHASE_SHIFT => 0,
      STARTUP_WAIT => FALSE)
     port map (
      CLKIN => CLKIN_IBUFG,
      CLKFB => CLKFB_IN,
      RST => RST_IN,
      PSEN => GND,
      PSINCDEC => GND,
      PSCLK => GND,
      DSSEN => GND,
      CLK0 => CLK0_BUF,
      CLKDV => CLKDV_BUF,
      CLK2X => CLK2X_BUF,
      LOCKED => LOCKED_OUT);

   CLKIN_IBUFG_INST : IBUFG
     port map (
      I => CLKIN_IN,
      O => CLKIN_IBUFG);

   CLK0_BUFG_INST : BUFG
     port map (
      I => CLK0_BUF,
      O => CLKFB_IN);

   CLK2X_BUFG_INST : BUFG
     port map (
      I => CLK2X_BUF,
      O => CLK2X_OUT);

   CLKDV_BUFG_INST : BUFG
     port map (
      I => CLKDV_BUF,
      O => CLKDV_OUT);

   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
   CLK0_OUT <= CLKFB_IN;
   GND <= '0';
end STRUCT;