c8051f320addr.h

基于C8051单片机的USB Device driver

sbit MASTER  = SMB0CN ^ 7; /* MASTER/SLAVE INDICATOR                                */

/*  TMR2CN 0xC8 */
sbit T2XCLK  = TMR2CN ^ 0; /* TIMER 2 EXTERNAL CLOCK SELECT                         */
sbit TR2     = TMR2CN ^ 2; /* TIMER 2 ON/OFF CONTROL                                */
sbit T2SPLIT = TMR2CN ^ 3; /* TIMER 2 SPLIT MODE ENABLE                             */
sbit TF2LEN  = TMR2CN ^ 5; /* TIMER 2 LOW BYTE INTERRUPT ENABLE                     */
sbit TF2L    = TMR2CN ^ 6; /* TIMER 2 LOW BYTE OVERFLOW FLAG                        */
sbit TF2H    = TMR2CN ^ 7; /* TIMER 2 HIGH BYTE OVERFLOW FLAG                       */

/*  PSW 0xD0 */
sbit P       = PSW ^ 0;    /* ACCUMULATOR PARITY FLAG                               */
sbit F1      = PSW ^ 1;    /* USER FLAG 1                                           */
sbit OV      = PSW ^ 2;    /* OVERFLOW FLAG                                         */
sbit RS0     = PSW ^ 3;    /* REGISTER BANK SELECT 0                                */
sbit RS1     = PSW ^ 4;    /* REGISTER BANK SELECT 1                                */
sbit F0      = PSW ^ 5;    /* USER FLAG 0                                           */
sbit AC      = PSW ^ 6;    /* AUXILIARY CARRY FLAG                                  */
sbit CY      = PSW ^ 7;    /* CARRY FLAG                                            */

/* PCA0CN 0xD8H */
sbit CCF0    = PCA0CN ^ 0; /* PCA0 MODULE 0 CAPTURE/COMPARE FLAG                    */
sbit CCF1    = PCA0CN ^ 1; /* PCA0 MODULE 1 CAPTURE/COMPARE FLAG                    */
sbit CCF2    = PCA0CN ^ 2; /* PCA0 MODULE 2 CAPTURE/COMPARE FLAG                    */
sbit CCF3    = PCA0CN ^ 3; /* PCA0 MODULE 3 CAPTURE/COMPARE FLAG                    */
sbit CCF4    = PCA0CN ^ 4; /* PCA0 MODULE 4 CAPTURE/COMPARE FLAG                    */
sbit CR      = PCA0CN ^ 6; /* PCA0 COUNTER RUN CONTROL                              */
sbit CF      = PCA0CN ^ 7; /* PCA0 COUNTER OVERFLOW FLAG                            */

/* ADC0CN 0xE8H */
sbit AD0CM0  = ADC0CN ^ 0; /* ADC0 CONVERSION MODE SELECT 0                         */
sbit AD0CM1  = ADC0CN ^ 1; /* ADC0 CONVERSION MODE SELECT 1                         */
sbit AD0CM2  = ADC0CN ^ 2; /* ADC0 CONVERSION MODE SELECT 2                         */
sbit AD0WINT = ADC0CN ^ 3; /* ADC0 WINDOW COMPARE INTERRUPT FLAG                    */
sbit AD0BUSY = ADC0CN ^ 4; /* ADC0 BUSY FLAG                                        */
sbit AD0INT  = ADC0CN ^ 5; /* ADC0 CONVERISION COMPLETE INTERRUPT FLAG              */
sbit AD0TM   = ADC0CN ^ 6; /* ADC0 TRACK MODE                                       */
sbit AD0EN   = ADC0CN ^ 7; /* ADC0 ENABLE                                           */

/* SPI0CN 0xF8H */
sbit SPIF    = SPI0CN ^ 7; /* SPI 0 INTERRUPT FLAG                                  */
sbit WCOL    = SPI0CN ^ 6; /* SPI 0 WRITE COLLISION FLAG                            */
sbit MODF    = SPI0CN ^ 5; /* SPI 0 MODE FAULT FLAG                                 */
sbit RXOVRN  = SPI0CN ^ 4; /* SPI 0 RX OVERRUN FLAG                                 */
sbit TXBSY   = SPI0CN ^ 3; /* SPI 0 SLAVE SELECT MODE 1                             */
sbit SLVSEL  = SPI0CN ^ 2; /* SPI 0 SLAVE SELECT MODE 0                             */
sbit TXBMT   = SPI0CN ^ 1; /* SPI 0 TRANSMIT BUFFER EMPTY                           */
sbit SPIEN   = SPI0CN ^ 0; /* SPI 0 SPI ENABLE                                      */

#ifndef _USB_REGISTER_H_
#define _USB_REGISTER_H_

// USB Core Registers
#define  BASE     0x00
#define  FADDR    BASE
#define  POWER    BASE + 0x01
#define  IN1INT   BASE + 0x02
#define  OUT1INT  BASE + 0x04
#define  CMINT    BASE + 0x06
#define  IN1IE    BASE + 0x07
#define  OUT1IE   BASE + 0x09
#define  CMIE     BASE + 0x0B
#define  FRAMEL   BASE + 0x0C
#define  FRAMEH   BASE + 0x0D
#define  INDEX    BASE + 0x0E
#define  CLKREC   BASE + 0x0F
#define  E0CSR    BASE + 0x11
#define  EINCSRL  BASE + 0x11
#define  EINCSRH  BASE + 0x12
#define  EOUTCSRL BASE + 0x14
#define  EOUTCSRH BASE + 0x15
#define  E0CNT    BASE + 0x16
#define  EOUTCNTL BASE + 0x16
#define  EOUTCNTH BASE + 0x17
#define  FIFO_EP0 BASE + 0x20
#define  FIFO_EP1 BASE + 0x21
#define  FIFO_EP2 BASE + 0x22
#define  FIFO_EP3 BASE + 0x23

// USB Core Register Bits

// POWER
#define  rbISOUD        0x80
#define  rbSPEED        0x40
#define  rbUSBRST       0x08
#define  rbRESUME       0x04
#define  rbSUSMD        0x02
#define  rbSUSEN        0x01

// IN1INT
#define  rbIN3          0x08
#define  rbIN2          0x04
#define  rbIN1          0x02
#define  rbEP0          0x01

// OUT1INT
#define  rbOUT3         0x08
#define  rbOUT2         0x04
#define  rbOUT1         0x02

// CMINT
#define  rbSOF          0x08
#define  rbRSTINT       0x04
#define  rbRSUINT       0x02
#define  rbSUSINT       0x01

// IN1IE
#define  rbIN3E         0x08
#define  rbIN2E         0x04
#define  rbIN1E         0x02
#define  rbEP0E         0x01

// OUT1IE
#define  rbOUT3E        0x08
#define  rbOUT2E        0x04
#define  rbOUT1E        0x02

// CMIE
#define  rbSOFE         0x08
#define  rbRSTINTE      0x04
#define  rbRSUINTE      0x02
#define  rbSUSINTE      0x01

// E0CSR
#define  rbSSUEND       0x80
#define  rbSOPRDY       0x40
#define  rbSDSTL        0x20
#define  rbSUEND        0x10
#define  rbDATAEND      0x08
#define  rbSTSTL        0x04
#define  rbINPRDY       0x02
#define  rbOPRDY        0x01

// EINCSR1
#define  rbInCLRDT      0x40
#define  rbInSTSTL      0x20
#define  rbInSDSTL      0x10
#define  rbInFLUSH      0x08
#define  rbInUNDRUN     0x04
#define  rbInFIFONE     0x02
#define  rbInINPRDY     0x01

// EINCSR2
#define  rbInDBIEN      0x80
#define  rbInISO        0x40
#define  rbInDIRSEL     0x20
#define  rbInFCDT       0x08
#define  rbInSPLIT      0x04

// EOUTCSR1
#define  rbOutCLRDT     0x80
#define  rbOutSTSTL     0x40
#define  rbOutSDSTL     0x20
#define  rbOutFLUSH     0x10
#define  rbOutDATERR    0x08
#define  rbOutOVRUN     0x04
#define  rbOutFIFOFUL   0x02
#define  rbOutOPRDY     0x01

// EOUTCSR2
#define  rbOutDBOEN     0x80
#define  rbOutISO       0x40

// Register read/write macros
#define READ_REGISTER(addr,target) while(USB0ADR & 0x80); USB0ADR = (0x80 | addr); while(USB0ADR & 0x80); target = USB0DAT
#define WRITE_REGISTER(addr,data) while(USB0ADR & 0x80); USB0ADR = addr; USB0DAT = data

#endif /* _USB_REGISTER_H_ */