decl7s.fit.rpt

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+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+---------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                       ;
+--------------------------------------------------------------------------------+------------+
; Name                                                                           ; Value      ;
+--------------------------------------------------------------------------------+------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff         ;
; Mid Wire Use - Fit Attempt 1                                                   ; 0          ;
; Mid Slack - Fit Attempt 1                                                      ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1                                            ; 8          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 8          ;
; LAB Count - Fit Attempt 1                                                      ; 2          ;
; Outputs per Lab - Fit Attempt 1                                                ; 3.500      ;
; Inputs per LAB - Fit Attempt 1                                                 ; 2.000      ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.000      ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:2        ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:2        ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:2        ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:2        ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:2        ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:2        ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:2        ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:2        ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:2        ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:2        ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:2        ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:2        ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:2        ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:2        ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:1;1:1    ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:2        ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:2        ;
; LEs in Chains - Fit Attempt 1                                                  ; 0          ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0          ;
; LABs with Chains - Fit Attempt 1                                               ; 0          ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0          ;
; Time - Fit Attempt 1                                                           ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016      ;
+--------------------------------------------------------------------------------+------------+


+--------------------------------------------------+
; Advanced Data - Placement                        ;
+-------------------------------------+------------+
; Name                                ; Value      ;
+-------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff         ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff         ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff         ;
; Mid Wire Use - Fit Attempt 1        ; 0          ;
; Mid Slack - Fit Attempt 1           ; 2147483639 ;
; Late Wire Use - Fit Attempt 1       ; 0          ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff         ;
; Time - Fit Attempt 1                ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016      ;
+-------------------------------------+------------+


+--------------------------------------------------+
; Advanced Data - Routing                          ;
+-------------------------------------+------------+
; Name                                ; Value      ;
+-------------------------------------+------------+
; Early Slack - Fit Attempt 1         ; 2147483639 ;
; Mid Slack - Fit Attempt 1           ; 2147483639 ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Late Wire Use - Fit Attempt 1       ; 0          ;
; Time - Fit Attempt 1                ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.015      ;
+-------------------------------------+------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Oct 29 10:43:35 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DECL7S -c DECL7S
Info: Selected device EP1C3T144C8 for design "DECL7S"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6T144C8 is compatible
Info: No exact pin location assignment(s) for 11 pins of 11 total pins
    Info: Pin LED7S[0] not assigned to an exact location on the device
    Info: Pin LED7S[1] not assigned to an exact location on the device
    Info: Pin LED7S[2] not assigned to an exact location on the device
    Info: Pin LED7S[3] not assigned to an exact location on the device
    Info: Pin LED7S[4] not assigned to an exact location on the device
    Info: Pin LED7S[5] not assigned to an exact location on the device
    Info: Pin LED7S[6] not assigned to an exact location on the device
    Info: Pin A[0] not assigned to an exact location on the device
    Info: Pin A[1] not assigned to an exact location on the device
    Info: Pin A[2] not assigned to an exact location on the device
    Info: Pin A[3] not assigned to an exact location on the device
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 11 (unused VREF, 3.30 VCCIO, 4 input, 7 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: