decl7s.sim.rpt

七段数码显示译码器设计

The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                    ;
+--------------------------------------------------------------+--------------------------------------------------------------+------------------+
; Node Name                                                    ; Output Port Name                                             ; Output Port Type ;
+--------------------------------------------------------------+--------------------------------------------------------------+------------------+
; |DECL7S|A[0]                                                 ; |DECL7S|A[0]                                                 ; out              ;
; |DECL7S|A[1]                                                 ; |DECL7S|A[1]                                                 ; out              ;
; |DECL7S|A[2]                                                 ; |DECL7S|A[2]                                                 ; out              ;
; |DECL7S|A[3]                                                 ; |DECL7S|A[3]                                                 ; out              ;
; |DECL7S|LED7S[0]                                             ; |DECL7S|LED7S[0]                                             ; pin_out          ;
; |DECL7S|LED7S[1]                                             ; |DECL7S|LED7S[1]                                             ; pin_out          ;
; |DECL7S|LED7S[2]                                             ; |DECL7S|LED7S[2]                                             ; pin_out          ;
; |DECL7S|LED7S[3]                                             ; |DECL7S|LED7S[3]                                             ; pin_out          ;
; |DECL7S|LED7S[4]                                             ; |DECL7S|LED7S[4]                                             ; pin_out          ;
; |DECL7S|LED7S[5]                                             ; |DECL7S|LED7S[5]                                             ; pin_out          ;
; |DECL7S|LED7S[6]                                             ; |DECL7S|LED7S[6]                                             ; pin_out          ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~0              ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~0              ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~1              ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~1              ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~2              ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~2              ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|result_node[0]~1 ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|result_node[0]~1 ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|result_node[0]   ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|result_node[0]   ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~4              ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~4              ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~5              ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~5              ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~6              ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~6              ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result112w~0   ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result112w~0   ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result112w~1   ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result112w~1   ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result112w     ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result112w     ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~8              ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~8              ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~9              ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~9              ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~10             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~10             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result129w~0   ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result129w~0   ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result129w~1   ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result129w~1   ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result129w     ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result129w     ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~12             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~12             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~13             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~13             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~14             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~14             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result145w~0   ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result145w~0   ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~15             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~15             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result145w~1   ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result145w~1   ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result145w     ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result145w     ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~17             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~17             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~18             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~18             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result60w~1    ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result60w~1    ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result60w      ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result60w      ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~20             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~20             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~21             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~21             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result61w~0    ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result61w~0    ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~22             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~22             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result61w~1    ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result61w~1    ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result61w      ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result61w      ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~24             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~24             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~25             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~25             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~26             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~26             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~27             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~27             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result62w~1    ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result62w~1    ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result62w      ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result62w      ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~29             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~29             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~30             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~30             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result63w~1    ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result63w~1    ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result63w      ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result63w      ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~32             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~32             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~33             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~33             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~34             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~34             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result74w~0    ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result74w~0    ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result74w~1    ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result74w~1    ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result74w      ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result74w      ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~36             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~36             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~38             ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|_~38             ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result95w~1    ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result95w~1    ; out0             ;
; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result95w      ; |DECL7S|lpm_mux:Mux6|mux_3ec:auto_generated|w_result95w      ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~0              ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~0              ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~1              ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~1              ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~2              ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~2              ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~3              ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~3              ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|result_node[0]~1 ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|result_node[0]~1 ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|result_node[0]   ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|result_node[0]   ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~4              ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~4              ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~5              ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~5              ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~6              ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~6              ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result112w~0   ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result112w~0   ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result112w~1   ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result112w~1   ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result112w     ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result112w     ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~8              ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~8              ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~10             ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~10             ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~11             ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~11             ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result129w~1   ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result129w~1   ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result129w     ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result129w     ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~12             ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~12             ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~13             ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~13             ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~14             ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~14             ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result145w~0   ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result145w~0   ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~15             ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~15             ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result145w~1   ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result145w~1   ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result145w     ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result145w     ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~16             ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~16             ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~17             ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~17             ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~18             ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~18             ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result60w~1    ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result60w~1    ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result60w      ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|w_result60w      ; out0             ;
; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~21             ; |DECL7S|lpm_mux:Mux5|mux_3ec:auto_generated|_~21             ; out0             ;