pinlvji.vhd

一个基于VHDL的有效位为8位的频率计

 library ieee;  
use ieee.std_logic_1164.all;  
use ieee.std_logic_unsigned.all;  
entity siplj1 is  
port(fsin,clk1:in std_logic;  
 cout:out std_logic;  
 dout1:out std_logic_vector(31 downto 0));  
end siplj1;  
architecture be_siplj1 of siplj1 is  
component cnt10  
 port(clk,clr,ena:in std_logic;  
 cq:out std_logic_vector(3 downto 0);  
 carry_out:out std_logic);  
end component;  
component feg32b  
 port(load:in std_logic;  
 din:in std_logic_vector(31 downto 0);  
 dout:out std_logic_vector(31 downto 0));  
end component;  
component testctl  
 port(clk:in std_logic;  
 tsten,clr_cnt:out std_logic;  
 load:out std_logic);  
end component;  
signal a,b,c,d1,d2,d3,d4,d5,d6,d7:std_logic;  
signal f:std_logic_vector(31 downto 0);  
begin  
u1:testctl port map(clk=>clk1,tsten=>a,clr_cnt=>b,load=>c);  
u2:cnt10 port map(fsin,b,a,f(3 downto 0),d1);  
u3:cnt10 port map(d1,b,a,f(7 downto 4),d2);  
u4:cnt10 port map(d2,b,a,f(11 downto 8),d3);  
u5:cnt10 port map(d3,b,a,f(15 downto 12),d4);  
u6:cnt10 port map(d4,b,a,f(19 downto 16),d5);  
u7:cnt10 port map(d5,b,a,f(23 downto 20),d6);  
u8:cnt10 port map(d6,b,a,f(27 downto 24),d7);  
u9:cnt10 port map(d7,b,a,f(31 downto 28),cout);  
u10:feg32b port map(c,f(31 downto 0),dout1(31 downto 0));  
end be_siplj1;  
library ieee;  
use ieee.std_logic_1164.all;  
use ieee.std_logic_unsigned.all;  
entity cnt10 is  
port(clk,ena,clr:in std_logic;  
 cq:out std_logic_vector(3 downto 0);  
 carry_out:out std_logic);  
end cnt10;  
architecture be_cnt10 of cnt10 is  
signal cq1:std_logic_vector(3 downto 0);  
begin  
process(clk,clr,ena)  
begin  
if clr='1' then  
 cq1<="0000";  
elsif clk'event and clk='1' then  
 if ena='1' then  
 if cq1="1001" then  
 cq1<="0000";  
 carry_out<='1';  
 else cq1<=cq1+1; 
 carry_out<='0';  
 end if;  
 end if;  
end if;  
end process;  
cq<=cq1;  
end be_cnt10;  
library ieee;  
use ieee.std_logic_1164.all;  
entity feg32b is  
 port(load:in std_logic;  
 din:in std_logic_vector(31 downto 0);  
 dout:out std_logic_vector(31 downto 0));  
end feg32b;  
architecture be_feg32b of feg32b is  
begin  
process(load,din)  
begin  
if load'event and load='1' then  
 dout<=din;  
 end if;  
end process;  
end be_feg32b;  
library ieee;  
use ieee.std_logic_1164.all;  
use ieee.std_logic_unsigned.all;  
entity testctl is  
 port(clk:in std_logic;  
 tsten,clr_cnt,load:out std_logic);  
end testctl;  
architecture be_testctl of testctl is  
signal div2clk:std_logic;  
begin  
process(clk)  
begin  
if clk'event and clk='1' then  
 div2clk<=NOT div2clk;  
end if;  
end process;  
process(clk,div2clk)  
begin  
if clk='0' and div2clk='0' then  
 clr_cnt<='1';  
else clr_cnt<='0';  
end if;  
end process;  
load<= NOT div2clk;  
tsten<=div2clk;  
end be_testctl;