📄 scalerdef.h
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//--------------------------------------------------
#define _P1_MPLL_M_C8 0xC8 // MPLL M Divider Register
//#define _P1_MPLL_N_C9 0xC9 // MPLL N Divider Register
//#define _P1_MPLL_CRNT_CA 0xCA // MPLL Current/Resistor Register
//#define _P1_MPLL_WD_CB 0xCB // MPLL Watch Dog Register
//#define _P1_MPLL_MISC_CC 0xCC // MPLL MISC Register
//--------------------------------------------------
// MCLK Spread Spectrum
//--------------------------------------------------
//#define _P1_MCLK_FINE_TUNE_OFFSET_MSB_CD 0xCD // Memory Clock Fine Tune Offset MSB
//#define _P1_MCLK_FINE_TUNE_OFFSET_LSB_CE 0xCE // Memory Clock Fine Tune Offset LSB
//#define _P1_MCLK_SPREAD_SPECTRUM_CF 0xCF // Memory Clock Spread Spectrum
//Address: P1-D0~P1-DF Reserved
#endif
/////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////Page 2: TMDS/HDCP/HDMI//////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//--------------------------------------------------
// TMDS Receiver(Page 2)
//--------------------------------------------------
//#define _P2_RESERVED_A0 0xA0 // P2 Reserved A0
#define _P2_TMDS_MEAS_SELECT_A1 0xA1 // TMDS Measure Select
#define _P2_TMDS_MEAS_RESULT0_A2 0xA2 // TMDS Measure Result0
#define _P2_TMDS_MEAS_RESULT1_A3 0xA3 // TMDS Measure Result1
#define _P2_TMDS_CTRL_A4 0xA4 // TMDS Control Register
#define _P2_CRC_OUTPUT_BYTE_2_A5 0xA5 // CRC Output Byte2
#define _P2_TMDS_OUTPUT_CTRL_A6 0xA6 // TMDS Output Control Register
#define _P2_POWER_ON_OFF_CTRL_A7 0xA7 // TMDS Power On/Off Control Register
#define _P2_ANALOG_COMMON_CTRL0_A8 0xA8 // Analog Common Control Register 0
#define _P2_ANALOG_COMMON_CTRL1_A9 0xA9 // Analog Common Control Register 1
#define _P2_ANALOG_BIAS_CTRL_AA 0xAA // Analog Bias Control Register
#define _P2_ANALOG_COMMON_CTRL2_AB 0xAB // Analog Common Control Register 2
#define _P2_Z0_CALIBRATION_CTRL_AC 0xAC // Z0 Calibration Control Register
#define _P2_CLOCK_PLL_SETTING_AD 0xAD // Clock PLL Setting
#define _P2_RGB_PLL_SETTING_AE 0xAE // R/G/B PLL Setting
#define _P2_WATCH_DOG_CTRL_AF 0xAF // Watch Dog Control Register
#define _P2_CDR_CTRL0_B0 0xB0 // CDR Control Register 0
#define _P2_CDR_CTRL1_B1 0xB1 // CDR Control Register 1
#define _P2_CDR_CTRL2_B2 0xB2 // CDR Control Register 2
#define _P2_UP_DOWN_ADJUSTING1_B3 0xB3 // Up/Down Adjusting 1
#define _P2_ADAPTIVE_EQUALIZER_B4 0xB4 // Adaptive Equalizer
#define _P2_UP_DOWN_CTRL0_B5 0xB5 // Up/Down Control Register 0
#define _P2_UP_DOWN_CTRL1_B6 0xB6 // Up/Down Control Register 1
#define _P2_UP_DOWN_CTRL2_B7 0xB7 // Up/Down Control Register 2
#define _P2_ADAPTIVE_EQUALIZER2_B8 0xB8 // Adaptive Equalizer accumulative threshold (LPF1)//731301
//#define _P2_ADAPTIVE_EQUALIZER3_B9 0xB9 // Adaptive Equalizer continuous threshold (LPF2)
//#define _P2_ADAPTIVE_EQUALIZE4_BA 0xBA // Adaptive Equalizer auto stop threshold
//--------------------------------------------------
// HDCP1.1(Port)
//--------------------------------------------------
#define _P2_HDCP_CTRL_C0 0xC0 // HDCP Control Register
#define _P2_DEVICE_KEY_ACCESS_PORT_C1 0xC1 // Device Key Access Port
#define _P2_HDCP_PORT_CTRL_C2 0xC2 // HDCP Port Control Register
#define _P2_HDCP_ADDR_PORT_C3 0xC3 // HDCP Address Port
#define _P2_HDCP_DATA_PORT_C4 0xC4 // HDCP Data Port
//Address: P2-C5~P2-C6 Reserved
//--------------------------------------------------
// HDMI(Port)
//--------------------------------------------------
#define _P2_HDMI_APC_C8 0xC8 //
#define _P2_HDMI_ADDR_PORT_C9 0xC9 // HDMI Address Port
#define _P2_HDMI_DATA_PORT_CA 0xCA // HDMI Data Port
#define _P2_HDMI_SR_CB 0xCB // HDMI Status Register
#define _P2_HDMI_GPVS_CC 0xCC // HDMI Packet Variation Status Register
#define _P2_HDMI_PSAP_CD 0xCD // HDMI Address For Packet Storage SRAM
#define _P2_HDMI_DSAP_CE 0xCE // HDMI Data For Packet Storage SRAM
//Address: P2-CF ~ P2-FF Reserved
#if(_SCALER_TYPE == _RTD3580D)
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Page 3: Reserved //////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//Reserved Page (Page 3)
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Page 4: Reserved //////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//Reserved Page (Page 4)
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Page 5: Reserved //////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//Reserved Page (Page 5)
#else
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////Page 3: LiveShowTM Control////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
#define _P3_LS_CTRL0_A1 0xA1 // Live Show Control Register0
#define _P3_LS_CTRL1_A2 0xA2 // Live Show Control Register1
//Address: P3-A3 Reserved
#define _P3_LS_CPRS_CTRL_A4 0xA4 // Live Show Compression Type Control Register
#define _P3_LS_TG_SIZE_H_A5 0xA5 // Live Show Target Size For Compression HByte
//#define _P3_LS_TG_SIZE_L_A6 0xA6 // Live Show Target Size For Compression LByte
#define _P3_LS_GRP_NUM_H_A7 0xA7 // Live Show Number Of Pixel Per Group To Be Analyzed And Compressed HByte
//#define _P3_LS_GRP_NUM_L_A8 0xA8 // Live Show Number Of Pixel Per Group To Be Analyzed And Compressed LByte
//#define _P3_LS_FAIL_CNT_H_A9 0xA9 // Live Show The Count Of Compression Fail HByte
//#define _P3_LS_FAIL_CNT_L_AA 0xAA // Live Show The Count Of Compression Fail LByte
//Address: P3-AB~P3-AD Reserved
#define _P3_LS_LUT_ROW_ADDR_AE 0xAE // Live Show LUT Row Address
#define _P3_LS_LUT_COL_ADDR_AF 0xAF // Live Show LUT Colunm Address
#define _P3_LS_LUT_DATA_B0 0xB0 // Live Show LUT Data Port
//#define _P3_LS_DELTA_GAIN_B1 0xB1 // Live Show Delta Gain Setting
//#define _P3_LS_UDST_THD_B2 0xB2 // Live Show Undershoot Threshold(2's Complement)
//#define _P3_LS_OVST_THD_B3 0xB3 // Live Show Overshoot Threshold
//#define _P3_LS_UDST_GAIN_B4 0xB4 // Live Show Undershoot Gain
//#define _P3_LS_OVST_GAIN_B5 0xB5 // Live Show Overshoot Gain
#define _P3_LS_STATUS0_B6 0xB6 // Live Show Status Register0
//#define _P3_LS_STATUS1_B7 0xB7 // Live Show Status Register1
//Address: P3-B8~P3-BF Reserved
#define _P3_LS_WTLVL_W_C0 0xC0 // Live Show Water Level Write Register
#define _P3_LS_WTLVL_R_C1 0xC1 // Live Show Water Level Read Register
#define _P3_LS_MEM_FIFO_RW_NUM_H_C2 0xC2 // The Read/Write Times Of Total Memory Access HByte
//#define _P3_LS_MEM_FIFO_RW_NUM_L_C3 0xC3 // The Read/Write Times Of Total Memory Access LByte
#define _P3_LS_MEM_FIFO_RW_LEN_C4 0xC4 // The Read/Write Number Of Words In Each Memory Access
#define _P3_LS_MEM_FIFO_RW_REMAIN_C5 0xC5 // The Read/Write Number Of Words At The Last Access. This Register Must Be 4X
#define _P3_LS_MEM_START_ADDR_H_C6 0xC6 // Start Address Of Live Show Memory Block HByte(Total 22/23 bits)
//#define _P3_LS_MEM_START_ADDR_M_C7 0xC7 // Start Address Of Live Show Memory Block MByte(Total 22/23 bits)
//#define _P3_LS_MEM_START_ADDR_L_C8 0xC8 // Start Address Of Live Show Memory Block LByte(Total 22/23 bits)
//#define _P3_LS_BIST_CTRL_C9 0xC9 // Live Show BIST Control Register
//#define _P3_LS_COMP_CHK_CA 0xCA // Live Show Decompression Previous Buffer Status Check
//#define _P3_LS_COMP_REOVFW_CB 0xCB // Reorder Buffer Overflow By Group Dummy Purge LSB
/////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////Page 4: SDRAM Control///////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
#define _P4_SDR_CTRL0_A1 0xA1 // SDRAM Control Register0
//#define _P4_SDR_CTRL1_A2 0xA2 // SDRAM Control Register1
//#define _P4_SDR_AREF_TIME_A3 0xA3 // SDRAM Auto Refresh Time
#define _P4_SDR_PRCG_A4 0xA4 // SDRAM Precharge Control Register
//#define _P4_SDR_MEM_TYPE_A5 0xA5 // SDRAM Memory Size Select
//#define _P4_SDR_SLEW_RATE_A6 0xA6 // SDRAM Slew Rate Control Register
//#define _P4_SDR_AREF_CNT_A7 0xA7 // Number Of Auto Refresh
//Address: P4-A8~P4-A9 Reserved
//#define _P4_SDR_RSC_AREF_AA 0xAA // SDRAM Arbiter Token Ring For Auto Refresh
//#define _P4_SDR_RSC_MCU_AB 0xAB // SDRAM Arbiter Token Ring For MCU
//#define _P4_SDR_RSC_CAP1_AC 0xAC // SDRAM Arbiter Token Ring For CAP1
//Address: P4-AD Reserved
//#define _P4_SDR_RSC_MAIN_AE 0xAE // SDRAM Arbiter Token Ring For Main
//Address: P4-AF Reserved
//#define _P4_SDR_RSC_RD_B0 0xB0 // SDRAM Arbiter Token Ring For RD
//#define _P4_SDR_RSC_WR_B1 0xB1 // SDRAM Arbiter Token Ring For WR
//Address: P4-B2~P4-B3 Reserved
//#define _P4_SDR_ABTR_STATUS0_B4 0xB4 // SDRAM Arbiter Status Register0
//#define _P4_SDR_ABTR_STATUS1_B5 0xB5 // SDRAM Arbiter Status Register1
//Address: P4-B6~P4-B7 Reserved
//#define _P4_SDR_ADDR_H_B8 0xB8 // SDRAM Access Address HByte
//#define _P4_SDR_ADDR_M_B9 0xB9 // SDRAM Access Address MByte
//#define _P4_SDR_ADDR_L_BA 0xBA // SDRAM Access Address LByte
//#define _P4_SDR_ACCESS_CMD_BB 0xBB // SDRAM Access Command
//#define _P4_SDR_DATA_BUF_BC 0xBC // SDRAM Data Buffer
//Address: P4-BD~P4-BF Reserved
#define _P4_SDR_CLK_DELAY_C0 0xC0 // SDRAM Clock Delay Control Register
#define _P4_SDR_CLK_DELAY0_C1 0xC1 // SDRAM Clock Delay Control Register0
//#define _P4_SDR_CLK_DELAY1_C2 0xC2 // SDRAM Clock Delay Control Register1
//#define _P4_SDR_CLK_DELAY2_C3 0xC3 // SDRAM Clock Delay Control Register2
//#define _P4_SDR_CLK_DELAY3_C4 0xC4 // SDRAM Clock Delay Control Register3
//Address: P4-C5~P4-DF Reserved
/////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////Page 5: SDR_FIFO Control/////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//#define _P5_SDRF_IN1_FIFO_STATUS_A1 0xA1 // SDRAM IN1 FIFO Status Register
//#define _P5_SDRF_MAIN_FIFO_STATUS_A2 0xA2 // SDRAM MAIN FIFO Status Register
//Address: P5-A3~P5-A7 Reserved
//#define _P5_SDRF_IN1_WATER_LEVEL_A8 0xA8 // SDRAM FIFO IN1 Water Level Register
//#define _P5_SDRF_IN1_WR_NUM_H_A9 0xA9 // Number Of Length To Fill In The SDR Memory HByte
//#define _P5_SDRF_IN1_WR_NUM_L_AA 0xAA // Number Of Length To Fill In The SDR Memory LByte
//#define _P5_SDRF_IN1_WR_LEN_AB 0xAB // Length Of Data To Fill In The SDR Memory Once (unit : 64 bit)
//#define _P5_SDRF_IN1_WR_REMAIN_AC 0xAC // The Remained Part That Can't Make A Complete Length (unit : 64 bit)
//#define _P5_SDRF_IN1_MEM_ADDR_H_AD 0xAD // The Initial Write Address Of SDR Memory HByte
//#define _P5_SDRF_IN1_MEM_ADDR_M_AE 0xAE // The Initial Write Address Of SDR Memory MByte
//#define _P5_SDRF_IN1_MEM_ADDR_L_AF 0xAF // The Initial Write Address Of SDR Memory LByte
//#define _P5_SDRF_IN1_LINE_STEP_H_B0 0xB0 // The Distance Between Two Lines Of SDR Memory HByte
//#define _P5_SDRF_IN1_LINE_STEP_L_B1 0xB1 // The Distance Between Two Lines Of SDR Memory LByte
//#define _P5_SDRF_IN1_BLOCK_STEP_H_B2 0xB2 // The Distance Between Two Blocks Of SDR Memory HByte
//#define _P5_SDRF_IN1_BLOCK_STEP_L_B3 0xB3 // The Distance Between Two Blocks Of SDR Memory LByte
//#define _P5_SDRF_IN1_BL2_ADDR_H_B4 0xB4 // Second Block Of SDR To Progress The Double Buffer. The Given Address Is The Absolute One HByte
//#define _P5_SDRF_IN1_BL2_ADDR_M_B5 0xB5 // Second Block Of SDR To Progress The Double Buffer. The Given Address Is The Absolute One MByte
//#define _P5_SDRF_IN1_BL2_ADDR_L_B6 0xB6 // Second Block Of SDR To Progress The Double Buffer. The Given Address Is The Absolute One LByte
//#define _P5_SDRF_IN1_LINE_NUM_H_B7 0xB7 // The Total Line Number Of One Image HByte (Total 12 bits)
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