📄 scalerdef.h
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// Low Voltage Reset (Page0)
//--------------------------------------------------
#define _P0_POWER_ON_RESET_F3 0xF3 // Negative Threshold Value For Power On Reset
//--------------------------------------------------
// Schmitt Trigger Control (Page0)
//--------------------------------------------------
#define _P0_HS_SCHMITT_TRIGGER_CTRL_F4 0xF4 // Schmitt Trigger Control Register
//Address: P0-F5 ~ P0-FF Reserved
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Page 1: PLL //////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//--------------------------------------------------
// DDS Setting For ADC PLL (Page1)
//--------------------------------------------------
#define _P1_PLL_DIV_CTRL_A0 0xA0 // PLL DIV Control Register
#define _P1_I_CODE_M_A1 0xA1 // I Code MByte
#define _P1_I_CODE_L_A2 0xA2 // I Code LByte
#define _P1_P_CODE_A3 0xA3 // P Code
//#define _P1_PFD_CALIBRATED_RESULTS_H_A4 0xA4 // PFD Calibrated Result HByte
//#define _P1_PFD_CALIBRATED_RESULTS_L_A5 0xA5 // PFD Calibrated Result LByte
//#define _P1_PE_MEASURE_H_A6 0xA6 // Phase Error Measure HByte
//#define _P1_PE_MEASURE_L_A7 0xA7 // Phase Error Measure LByte
//#define _P1_PE_MAX_MEASURE_H_A8 0xA8 // Phase Error Max MEasure HByte
//#define _P1_PE_MAX_MEASURE_L_A9 0xA9 // Phase Error Max MEasure LByte
#define _P1_FAST_PLL_CTRL_AA 0xAA // Fast PLL Control Register
#define _P1_FAST_PLL_ISUM_AB 0xAB // Fast PLL I_SUM
//--------------------------------------------------
// ADC PLL (Page1)
//--------------------------------------------------
#define _P1_PLL_M_AC 0xAC // PLL M code
#define _P1_PLL_N_AD 0xAD // PLL N Code
#define _P1_PLL_CRNT_AE 0xAE // PLL Current/Resistor Register
#define _P1_PLL_WD_AF 0xAF // PLL Watch Dog Register
#define _P1_MIX_B0 0xB0 // PLL Mix Register
#define _P1_PLLDIV_H_B1 0xB1 // PLL DIV HByte
#define _P1_PLLDIV_L_B2 0xB2 // PLL DIV LByte
//#define _P1_PLLPHASE_CTRL0_B3 0xB3 // PLL Phase Control Register0
#define _P1_PLLPHASE_CTRL1_B4 0xB4 // PLL Phase Control Register1
#define _P1_PLL_PHASE_INTERPOLATION_B5 0xB5 // PLL Phase Interpolation
#define _P1_P_CODE_MAPPING_METHOD_B6 0xB6 // P Code Mapping Method
#define _P1_PE_TRACKING_METHOD_B7 0xB7 // PE Tracking Method
#define _P1_DDS_MIX_1_B8 0xB8 // DDS Mix 1
#define _P1_DDS_MIX_2_B9 0xB9 // DDS Mix 2
#define _P1_DDS_MIX_3_BA 0xBA // DDS Mix 3
//#define _P1_DDS_MIX_4_BB 0xBB // DDS Mix 4
//#define _P1_DDS_MIX_5_BC 0xBC // DDS Mix 5
//#define _P1_DDS_MIX_6_BD 0xBD // DDS Mix 6
//#define _P1_DDS_MIX_7_BE 0xBE // DDS Mix 7
//--------------------------------------------------
// DPLL (Page1)
//--------------------------------------------------
#define _P1_DPLL_M_BF 0xBF // DPLL M Divider
#define _P1_DPLL_N_C0 0xC0 // DPLL N Divider
#define _P1_DPLL_CRNT_C1 0xC1 // DPLL Current/Resistor Register
//--------------------------------------------------
// DCLK Spread Spectrum (Page1)
//--------------------------------------------------
#define _P1_DPLL_WD_C2 0xC2 // DPLL Watch Dog Register
#define _P1_DPLL_OTHER_C3 0xC3 // DPLL Other Register
#define _P1_DCLK_FINE_TUNE_OFFSET_MSB_C4 0xC4 // Display Clock Fine Tune Offset MSB
#define _P1_DCLK_FINE_TUNE_OFFSET_LSB_C5 0xC5 // Display Clock Fine Tune Offset LSB
#define _P1_DCLK_SPREAD_SPECTRUM_C6 0xC6 // Display Clock Spread Spectrum
#define _P1_EVEN_FIX_LASTLINE_M_C7 0xC7 // Even Fixed Last Line MSB
#define _P1_EVEN_FIX_LASTLINE_DVTOTAL_L_C8 0xC8 // Even Fixed Last Line DVTotal LSB
#define _P1_EVEN_FIX_LASTLINE_LENGTH_L_C9 0xC9 // Even Fixed Last Line Length LSB
#define _P1_EVEN_FIXED_LAST_LINE_CTRL_CA 0xCA // Fixed Last Line Control Register
//Address: P1-C4 ~ P1-CF Reserved
//--------------------------------------------------
// Multiply PLL For Input Crystal (Page1)
//--------------------------------------------------
#define _P1_MULTIPLY_PLL_CTRL0_E0 0xE0 // M2PLL Control Register0
#define _P1_MULTIPLY_PLL_CTRL1_E1 0xE1 // M2PLL Control Register1
//#define _P1_RESERVED_E2 0xE2 // P1 Reserved E2
//#define _P1_RESERVED_E3 0xE3 // P1 Reserved E3
#define _P1_MULTIPLY_POWER_DOWN_E4 0xE4 // M2PLL Power Down
//Address: P1-E5 ~ P1-E9 Reserved
//#define _P1_PLL_CHARGE_PUMP_CURRENT_0_EA 0xEA // PLL Charge Pump Current 0
#define _P1_LOOP_FILTER_CAPACITOR_EB 0xEB // PLL Loop Filter Capacitor
//#define _P1_PLL_CHARGE_PUMP_CURRENT_2_EC 0xEC // PLL Charge Pump Current 2
//Address: P1-ED ~ P1-FF Reserved
#else
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Page 0: Embedded ADC //////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
#define _P0_ADC_CTRL_A1 0xA1 // ADC Control Register
#define _P0_ADC_RED_CTL_A2 0xA2 // ADC Red Channel Control Register
#define _P0_ADC_GREEN_CTL_A3 0xA3 // ADC Green Channel Control Register
#define _P0_ADC_BLUE_CTL_A4 0xA4 // ADC Blue Channel Control Register
#define _P0_RED_GAIN_A5 0xA5 // ADC Red Channel Gain Adjust
#define _P0_RED_OFFSET_A8 0xA8 // ADC Red Channel Offset Adjust
#define _P0_SOG0_CTRL_AB 0xAB // SOG Control Register0
#define _P0_SOG1_CTRL_AC 0xAC // SOG Control Register1
#define _P0_ADC_POWER_AD 0xAD // ADC Power Control Register
#define _P0_ADC_CLOCK_CTRL_AE 0xAE // ADC Clock Control Register
#define _P0_ADC_TEST_CTRL_AF 0xAF // ADC Test Control Register
#define _P0_ADC_V_BAIS1_B2 0xB2 // ADC Bais Voltage Control Register1
//Address: P0-B9~P0-BF Reserved
//--------------------------------------------------
// Auto Black Level
//--------------------------------------------------
#define _P0_AUTO_BLACK_LEVEL_CTRL1_C0 0xC0 // Auto Black Level Control Register1
#define _P0_AUTO_BLACK_LEVEL_CTRL2_C1 0xC1 // Auto Black Level Control Register2
#define _P0_AUTO_BLACK_LEVEL_CTRL3_C2 0xC2 // Auto Black Level Control Register3
#define _P0_AUTO_BLACK_LEVEL_CTRL4_C3 0xC3 // Auto Black Level Control Register4
#define _P0_AUTO_BLACK_LEVEL_CTRL5_C4 0xC4 // Auto Black Level Control Register5
#define _P0_AUTO_BLACK_LEVEL_CTRL6_C5 0xC5 // Auto Black Level Control Register6
//Address: P0-C6~P0-C7 Reserved
#define _P0_AUTO_BLACK_LEVEL_R_VALUE_C8 0xC8 // Average Value of Red Channel in Test Mode
#define _P0_AUTO_BLACK_LEVEL_G_VALUE_C9 0xC9 // Average Value of Green Channel in Test Mode
#define _P0_AUTO_BLACK_LEVEL_B_VALUE_CA 0xCA // Average Value of Blue Channel in Test Mode
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Page 1: PLL //////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////
//--------------------------------------------------
// DDS Setting For ADC PLL
//--------------------------------------------------
#define _P1_PLL_DIV_CTRL_A1 0xA1 // PLL DIV Control Register
//#define _P1_I_CODE_L_A2 0xA2 // I Code LByte
#define _P1_I_CODE_M_A3 0xA3 // I Code MByte
//#define _P1_P_CODE_A4 0xA4 // P Code
//#define _P1_PFD_CALIBRATED_RESULTS_A5 0xA5 // PFD Calibrated Result
//#define _P1_PE_MEASURE_A6 0xA6 // Phase Error Measure
//#define _P1_PE_MAX_MEASURE_A7 0xA7 // Phase Error Max MEasure
#define _P1_FAST_PLL_CTRL_A8 0xA8 // Fast PLL Control Register
#define _P1_FAST_PLL_ISUM_A9 0xA9 // Fast PLL I_SUM
//--------------------------------------------------
// ADC PLL1
//--------------------------------------------------
#define _P1_PLL1_M_AA 0xAA // PLL1 M code
#define _P1_PLL1_N_AB 0xAB // PLL1 N Code
//#define _P1_PLL1_CRNT_AC 0xAC // PLL1 Current/Resistor Register
//#define _P1_PLL1_WD_AD 0xAD // PLL1 Watch Dog Register
//--------------------------------------------------
// ADC PLL2
//--------------------------------------------------
#define _P1_PLL2_M_AE 0xAE // PLL2 M code
#define _P1_PLL2_N_AF 0xAF // PLL2 N code
#define _P1_PLL2_CRNT_B0 0xB0 // PLL2 Current/Resistor Register
#define _P1_PLL2_WD_B1 0xB1 // PLL2 Watch Dog Register
#define _P1_PLLDIV_H_B2 0xB2 // PLL DIV HByte
#define _P1_PLLDIV_L_B3 0xB3 // PLL DIV LByte
//#define _P1_PLLPHASE_CTRL0_B4 0xB4 // PLL Phase Control Register0
#define _P1_PLLPHASE_CTRL1_B5 0xB5 // PLL Phase Control Register1
#define _P1_PLL2_PHASE_INTERPOLATION_B6 0xB6 // PLL2 Phase Interpolation
//--------------------------------------------------
// DPLL
//--------------------------------------------------
#define _P1_DPLL_M_B7 0xB7 // DPLL M Divider
#define _P1_DPLL_N_B8 0xB8 // DPLL N Divider
//#define _P1_DPLL_CRNT_B9 0xB9 // DPLL Current/Resistor Register
#define _P1_DPLL_WD_BA 0xBA // DPLL Watch Dog Register
#define _P1_DPLL_OTHER_BB 0xBB // DPLL Other Register
//--------------------------------------------------
// DCLK Spread Spectrum
//--------------------------------------------------
#define _P1_DCLK_FINE_TUNE_OFFSET_MSB_BC 0xBC // Display Clock Fine Tune Offset MSB
#define _P1_DCLK_FINE_TUNE_OFFSET_LSB_BD 0xBD // Display Clock Fine Tune Offset LSB
#define _P1_DCLK_SPREAD_SPECTRUM_BE 0xBE // Display Clock Spread Spectrum
#define _P1_FIXED_LAST_LINE_MSB_BF 0xBF // Fixed Last Line MSB
//#define _P1_FIXED_LAST_LINE_DVTOTAL_LSB_C0 0xC0 // Fixed Last Line DVTotal LSB
//#define _P1_FIXED_LAST_LINE_LENGTH_LSB_C1 0xC1 // Fixed Last Line Length LSB
#define _P1_FIXED_LAST_LINE_CTRL_C2 0xC2 // Fixed Last Line Control Register
//Address: C3 Reserved
//--------------------------------------------------
// Multiply PLL For Input Crystal
//--------------------------------------------------
#define _P1_MULTIPLY_PLL_CTRL0_C4 0xC4 // Multiply PLL Control Register0
//#define _P1_MULTIPLY_PLL_CTRL1_C5 0xC5 // Multiply PLL Control Register1
//Address: C6,C7 Reserved
//--------------------------------------------------
// Memory PLL
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