📄 scalerdef.h
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#endif
//--------------------------------------------------
// Overlay/Color Palette/Background Color Control
//--------------------------------------------------
#define _OVERLAY_CTRL_6C 0x6C // Overlay Display Control Register
#define _BGND_COLOR_CTRL_6D 0x6D // Background Color Control Register
#define _OVERLAY_LUT_ADDR_6E 0x6E // Overlay Look Up Table (LUT) Address
#define _COLOR_LUT_PORT_6F 0x6F // Color LUT Access Port
//--------------------------------------------------
// Image Auto Function
//--------------------------------------------------
#define _H_BOUNDARY_H_70 0x70 // Horizontal Start/End Boundary HByte
#define _H_BOUNDARY_STA_L_71 0x71 // Horizontal Start Boundary HByte
#define _H_BOUNDARY_END_L_72 0x72 // Horizontal End Boundary HByte
#define _V_BOUNDARY_H_73 0x73 // Vertical Start/End Boundary HByte
#define _V_BOUNDARY_STA_L_74 0x74 // Vertical Start Boundary LByte
#define _V_BOUNDARY_END_L_75 0x75 // Vertical End Boundary LByte
#define _RED_NOISE_MARGIN_76 0x76 // Red Noise Margin Control Register
#define _GRN_NOISE_MARGIN_77 0x77 // Green Noise Margin Control Register
#define _BLU_NOISE_MARGIN_78 0x78 // Blue Noise Margin Control Register
#define _DIFF_THRESHOLD_79 0x79 // Difference Threshold
#define _AUTO_ADJ_CTRL0_7A 0x7A // Auto Adjusting Control Register 0
#define _HW_AUTO_PHASE_CTRL0_7B 0x7B // Hardware Auto Phase Control Register 0
#define _HW_AUTO_PHASE_CTRL1_7C 0x7C // Hardware Auto Phase Control Register 1
#define _AUTO_ADJ_CTRL1_7D 0x7D // Auto Adjusting Control Register 1
#define _V_START_END_H_7E 0x7E // Actuve Region Vertical Start/End HByte
#define _V_START_L_7F 0x7F // Actuve Region Vertical Start LByte
#define _V_END_L_80 0x80 // Actuve Region Vertical End LByte
#define _H_START_END_H_81 0x81 // Actuve Region Horizontal Start/End HByte
#define _H_START_L_82 0x82 // Actuve Region Horizontal Start LByte
#define _H_END_L_83 0x83 // Actuve Region Horizontal End LByte
#define _AUTO_PHASE_3_84 0x84 // Auto Phase Result Register Byte 3
#define _AUTO_PHASE_2_85 0x85 // Auto Phase Result Register Byte 2
#define _AUTO_PHASE_1_86 0x86 // Auto Phase Result Register Byte 1
#define _AUTO_PHASE_0_87 0x87 // Auto Phase Result Register Byte 0
//Address: 88~8A Reserved
//--------------------------------------------------
// Embedded Timing Controller(Port)
//--------------------------------------------------
#define _TCON_ADDR_PORT_8B 0x8B // TCON Address Port for Embedded TCON Access
#define _TCON_DATA_PORT_8C 0x8C // TCON Data Port for Embedded TCON Access
//
#define _LVDS_CTRL0_A0 0xA0 //
#define _LVDS_CTRL1_A1 0xA1 //
#define _LVDS_CTRL2_A2 0xA2 //
#define _LVDS_CTRL3_A3 0xA3 //
#define _LVDS_CTRL4_A4 0xA4 //
#define _LVDS_CTRL5_A5 0xA5 //
//--------------------------------------------------
// Pin Configuration(Port)
//--------------------------------------------------
#define _PS_ACCESS_PORT_8D 0x8D // Pin Share Access Port
#define _PS_DATA_PORT_8E 0x8E // Pin Share Data Port
//Address: 8F Reserved
//--------------------------------------------------
// Embedded OSD
//--------------------------------------------------
#define _OSD_ADDR_MSB_90 0x90 // OSD Address MSB
#define _OSD_ADDR_LSB_91 0x91 // OSD Address LSB
#define _OSD_DATA_PORT_92 0x92 // OSD Data Port
#define _OSD_SCRAMBLE_93 0x93 // OSD Scramble
#define _OSD_TEST_94 0x94 // OSD Test
//Address: 95~97 Reserved
//--------------------------------------------------
// Digital Filter
//--------------------------------------------------
#define _DIGITAL_FILTER_CTRL_98 0x98 // Digital Filter Control Register
#define _DIGITAL_FILTER_PORT_99 0x99 // Digital Filter Port
//--------------------------------------------------
// Peaking Filter and Coring Control(Port)
//--------------------------------------------------
#define _PC_ACCESS_PORT_9A 0x9A // Peaking/Coring Access Port
#define _PC_DATA_PORT_9B 0x9B // Peaking/Coring Data Port
//--------------------------------------------------
// Video Color Space Conversion
//--------------------------------------------------
#define _YUV2RGB_CTRL_9C 0x9C // YUV to RGB Control Register
#define _YUV_RGB_COEF_DATA_9D 0x9D // YUV to RGB Coefficient Data Port
//Address:9E~9F Reserved
#if(_SCALER_TYPE == _RTD3580D)
//--------------------------------------------------
// VBI(Port)
//--------------------------------------------------
#define _VBI_ACCESS_PORT_9A 0x9A // VBI Access Port
#define _VBI_DATA_PORT_9B 0x9B // VBI Data Port
#endif
////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////
//PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE
//PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE
//PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE
//--------------------------------------------------
// Paged Control Register
//--------------------------------------------------
#if(_SCALER_TYPE == _RTD3580D)
#define _PAGE_SELECT_9F 0x9F // Page Selector (CRA0~CRFF)
#else
#define _PAGE_SELECT_A0 0xA0 // Page Selector (CRA1~CRDF)
#endif
#if(_SCALER_TYPE == _RTD3580D)
//--------------------------------------------------
// Video ADC (Page0)
//--------------------------------------------------
#define _P0_VADC_SOY_COMPAR_A0 0xA0 // VADC SOY Comparator Select
#define _P0_VADC_CTRL_A1 0xA1 // VADC Control Register
#define _P0_VADC_CLOCK_A2 0xA2 // VADC Clock Source
#define _P0_VADC_OUTPUT_DELAY_A3 0xA3 // VADC Output Delay
//#define _P0_RESERVED_A4 0xA4 // P0 Reserved A4
#define _P0_VADC_INPUT_BW_A5 0xA5 // VADC Input BW
#define _P0_VADC1_INPUT_PGA_A6 0xA6 // VADC1 Input PGA
#define _P0_VADC0_INPUT_PGA_A7 0xA7 // VADC0 Input PGA
#define _P0_VADC_CLAMP_A8 0xA8 // VADC Clamp
#define _P0_VADC_INRANGE_A9 0xA9 // VADC Input Range
//#define _P0_RESERVED_AA 0xAA // P0 Reserved AA
#define _P0_VADC1_SOY_BIAS_CUR_AB 0xAB // VADC1 SOY Bias Current
#define _P0_VADC_IN_CH_BIAS_CUR_AC 0xAC // VADC Input Channel Bias Current
#define _P0_VADC_POS_IN_SOY_RES_AD 0xAD // VADC Posive Input SOY Restore Resistor
#define _P0_VADC_CLAMP_POWER_AE 0xAE // VADC Clamp Power
#define _P0_VADC_SWITCH_AF 0xAF // VADC/Video8 Switch
//--------------------------------------------------
// YPbPr ADC (Page0)
//--------------------------------------------------
#define _P0_RED_GAIN_C0 0xC0 // ADC Red Channel Gain Adjust
#define _P0_GRN_GAIN_C1 0xC1 // ADC Green Channel Gain Adjust
#define _P0_BLU_GAIN_C2 0xC2 // ADC Blue Channel Gain Adjust
#define _P0_RED_OFFSET_C3 0xC3 // ADC Red Channel Offset Adjust
#define _P0_GRN_OFFSET_C4 0xC4 // ADC Green Channel Offset Adjust
#define _P0_BLU_OFFSET_C5 0xC5 // ADC Blue Channel Offset Adjust
#define _P0_ADC_POWER_C6 0xC6 // ADC Power Control Register
#define _P0_ADC_I_BAIS0_C7 0xC7 // ADC Bais Current Control Register0
#define _P0_ADC_I_BAIS1_C8 0xC8 // ADC Bais Current Control Register1
#define _P0_ADC_I_BAIS2_C9 0xC9 // ADC Bais Current Control Register2
#define _P0_ADC_V_BAIS0_CA 0xCA // ADC Bais Voltage Control Register0
#define _P0_ADC_V_BAIS1_CB 0xCB // ADC Bais Voltage Control Register1
#define _P0_ADC_CLOCK_CTRL_CC 0xCC // ADC Clock Control Register
#define _P0_ADC_TEST_CTRL_CD 0xCD // ADC Test Control Register
#define _P0_ADC_RBG_CTRL_CE 0xCE // ADC RGB Control Register
#define _P0_ADC_RED_CTL_CF 0xCF // ADC Red Channel Control Register
#define _P0_ADC_GREEN_CTL_D0 0xD0 // ADC Green Channel Control Register
#define _P0_ADC_BLUE_CTL_D1 0xD1 // ADC Blue Channel Control Register
#define _P0_ADC_SOG0_CTRL_D2 0xD2 // ADC SOG0 Reference Control Register
#define _P0_ADC_DCR_CTRL_D3 0xD3 // ADC DCR Reference Control Register
#define _P0_ADC_CLAMP_CTRL0_D4 0xD4 // ADC Clamp Control Register0
#define _P0_ADC_CLAMP_CTRL1_D5 0xD5 // ADC Clamp Control Register1
#define _P0_ADC_SOG_CTRL_D6 0xD6 // ADC SOG Control Register
//#define _P0_TEST_PTN_POS_H_D7 0xD7 // Test Pattern H/V Position HByte
//#define _P0_TEST_PTN_VPOS_L_D8 0xD8 // Assign the test pattern digitized position(LByte) in line after V_Start.
//#define _P0_TEST_PTN_HPOS_L_D9 0xD9 // Assign the test pattern digitized position(LByte) in line after H_Start.
//#define _P0_TEST_PTN_RD_DA 0xDA // Test Pattern Red Channel Digitized Result
//#define _P0_TEST_PTN_GD_DB 0xDB // Test Pattern Green Channel Digitized Result
//#define _P0_TEST_PTN_BD_DC 0xDC // Test Pattern Blue Channel Digitized Result
//--------------------------------------------------
// Auto Black Level (Page0)
//--------------------------------------------------
#define _P0_ABL_CTRL1_E2 0xE2 // Auto Black Level Control Register1
#define _P0_ABL_CTRL2_E3 0xE3 // Auto Black Level Control Register2
#define _P0_ABL_CTRL3_E4 0xE4 // Auto Black Level Control Register3
#define _P0_ABL_CTRL4_E5 0xE5 // Auto Black Level Control Register4
#define _P0_ABL_CTRL5_E6 0xE6 // Auto Black Level Control Register5
#define _P0_ABL_CTRL6_E7 0xE7 // Auto Black Level Control Register6
#define _P0_ABL_CTRL7_E8 0xE8 // Auto Black Level Control Register6
//#define _P0_ABL_R_VALUE_E9 0xE9 // Auto Black Level Value of Red Channel in Test Mode
//#define _P0_ABL_G_VALUE_EA 0xEA // Auto Black Level Value of Green Channel in Test Mode
//#define _P0_ABL_B_VALUE_EB 0xEB // Auto Black Level Value of Blue Channel in Test Mode
//#define _P0_ABL_R_NOISE_VALUE_EC 0xEC // Auto Black Level Noise Value of Red Channel in Test Mode
//#define _P0_ABL_G_NOISE_VALUE_ED 0xED // Auto Black Level Noise Value of Green Channel in Test Mode
//#define _P0_ABL_B_NOISE_VALUE_EE 0xEE // Auto Black Level Noise Value of Blue Channel in Test Mode
//Address: P0-EF ~ P0-F2 Reserved
//--------------------------------------------------
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