scalerdef.h

RTD2662板卡源代码

//----------------------------------------------------------------------------------------------------
// ID Code      : ScalerDef.h No.0000
// Update Note  :
//
//----------------------------------------------------------------------------------------------------
//--------------------------------------------------
// Definitions of RTD2528R Control Register Address
//--------------------------------------------------

//--------------------------------------------------
// Global Event Flag
//--------------------------------------------------
#define _ID_REG_00                          	0x00        // ID Code Register
#define _HOST_CTRL_01                       	0x01        // Host Control Register
#define _STATUS0_02                         	0x02        // Status0 Register
#define _STATUS1_03                         	0x03        // Status1 Register
#define _IRQ_CTRL0_04                       	0x04        // IRQ Control Register0
#define _HDMI_STATUS0_05                    	0x05        // HDMI Status0 Register
#if(_SCALER_TYPE == _RTD3580D)
#define _NEW_ADDED_STATUS0_07        			0x07        // NEW Added Status0 Register
#define _NEW_ADDED_STATUS1_08					0x08        // NEW Added Status1 Register
#endif

//#define _HDMI_STATUS1_06                    		0x06        // HDMI Status1 Register
//Address: 07~0B Reserved
#define _WATCH_DOG_CTRL0_0C              		0x0C        // Watch Dog Control Register0
#define _WATCH_DOG_CTRL1_0D         			0x0D        // Watch Dog Control Register1
//Address: 0E~0F Reserved
#define _VGIP_CTRL_10                       	0x10        // Video Graphic Input Port(VGIP) Control Register
#define _VGIP_SIGINV_11                     	0x11        // Input Control Signal Inverted Register
#define _VGIP_DELAY_CTRL_12                 	0x12        // VGIP Delay Control Register
#define _VGIP_ODD_CTRL_13                   	0x13        // VGIP Odd Control Register

//--------------------------------------------------
// Input Frame Window
//-------------------------------------------------
#define _IPH_ACT_STA_H_14                   	0x14        // Input Horizontal Active Start HByte
#define _IPH_ACT_STA_L_15                   	0x15        // Input Horizontal Active Start LByte
#define _IPH_ACT_WID_H_16                   	0x16        // Input Horizontal Active Width HByte
#define _IPH_ACT_WID_L_17                   	0x17        // Input Horizontal Active Width LByte
#define _IPV_ACT_STA_H_18                   	0x18        // Input Vertical Active Start HByte
#define _IPV_ACT_STA_L_19                   	0x19        // Input Vertical Active Start LByte
#define _IPV_ACT_LEN_H_1A                   	0x1A        // Input Vertical Active Length HByte
#define _IPV_ACT_LEN_L_1B                   	0x1B        // Input Vertical Active Length LByte
#define _IVS_DELAY_1C                       	0x1C        // Internal Input Vertical Sync(VS) Delay Control Register
#define _IHS_DELAY_1D                       	0x1D        // Internal Input Horizontal Sync(HS) Delay Control Register
#define _VGIP_HV_DELAY_1E                   	0x1E        // VGIP HS/VS Delay
#if(_SCALER_TYPE == _RTD3580D)
#define _IPH_PORCH_NUM_H_1F         			0x1F        // Input Video Horizontal Porch HByte
#define _IPH_PORCH_NUM_L_20                		0x20        // Input Video Horizontal Porch LByte
#endif

#if(_SCALER_TYPE == _RTD3580D)
//--------------------------------------------------
// FIFO Frequency
//--------------------------------------------------
#define _FIFO_FREQUENCY_22                  	0x22        // FIFO Frequency

//--------------------------------------------------
// Input Pattern Generator
//--------------------------------------------------
#define _FIFO_BIST_CTRL_23                  	0x23        // FIFO BIST Control Register
#define _INPUT_PAT_GEN_ACCESS_PORT_24  			0x24        // Input Pattern Generator Access Port
#define _INPUT_PAT_GEN_DATA_PORT_25      		0x25        // Input Pattern Generator Data Port
//#define _RESERVED_26                        0x26       // Reserved 26
//#define _RESERVED_27                        0x27        // Reserved 27
#else
//--------------------------------------------------
// FIFO Frequency
//--------------------------------------------------
#define _FIFO_FREQUENCY_22                  	0x22        // FIFO Frequency
#define _SCALE_DOWN_CTRL_23                 	0x23        // Scale Down Control Register

//--------------------------------------------------
// Scale Down Function(Port)
//--------------------------------------------------
#define _SD_ACCESS_PORT_24                  	0x24        // Scale Down Access Port
#define _SD_DATA_PORT_25                    	0x25        // Scale Down Data Port
//Address: 26~27 Reserved
#endif

//--------------------------------------------------
// Display Format(Port)
//--------------------------------------------------
#define _VDISP_CTRL_28                      	0x28        // Video Display Control Register
#define _VDISP_SIGINV_29                    	0x29        // Display Control Signal Inverted Register
#define _DISP_ACCESS_PORT_2A              		0x2A        // Display Format Access Port
#define _DISP_DATA_PORT_2B                  	0x2B        // Display Format Data Port
#if(_SCALER_TYPE == _RTD3580D)
#define _OP_CRC_CTRL_2C                     	0x2C        // Output CRC Control Register 
#define _OP_CRC_CHECKSUM_2D               		0x2D        // Output CRC Checksum
#endif
//Address: 2C~2F Reserved

//--------------------------------------------------
// FIFO Window(Port)
//--------------------------------------------------
#define _FIFO_ACCESS_PORT_30                	0x30        // FIFO Window Address Port
#define _FIFO_DATA_PORT_31                  	0x31        // FIFO Window Data Port

//--------------------------------------------------
// Scale Up Function(Port)
//--------------------------------------------------
#define _SCALE_CTRL_32                      	0x32        // Scale Control Register
#define _SU_ACCESS_PORT_33                  	0x33        // Scale Up Factor Access Port
#define _SU_DATA_PORT_34                    	0x34        // Scale Up Factor Data Port
#define _FILTER_CTRL_35                     	0x35        // Filter Control Register
#define _FILTER_ACCESS_PORT_36              	0x36        // User Defined Filter Access Port
//Address: 37~3F Reserved

//--------------------------------------------------
// Frame Sync Fine Tune
//--------------------------------------------------
#define _IVS2DVS_DELAY_LINES_40             	0x40        // IVS to DVS Delay Lines
#define _IV_DV_DELAY_CLK_ODD_41           		0x41        // Frame Sync Delay Fine Tuning ODD
#define _IV_DV_DELAY_CLK_EVEN_42         		0x42        // Frame Sync Delay Fine Tuning EVEN
#define _FS_DELAY_FINE_TUNING_43        		0x43        // Frame Sync Delay Fine Tuning Control Register
#define _LAST_LINE_H_44                     	0x44        // Last Line HByte
#define _LAST_LINE_L_45                     	0x45        // Last Line LByte
//Address: 46 Reserved

//--------------------------------------------------
// Sync Processor(Port)
//--------------------------------------------------
#define _SYNC_SELECT_47                     	0x47        // Sync Select Control Register
#define _SYNC_INVERT_48                     	0x48        // Sync Invert Control Register
#define _SYNC_CTRL_49                       	0x49        // Sync Processor Control Register
#define _STABLE_HIGH_PERIOD_H_4A         		0x4A        // Stable High Period HByte
#define _STABLE_HIGH_PERIOD_L_4B         		0x4B        // Stable High Period LByte
#define _VSYNC_COUNTER_LEVEL_MSB_4C  			0x4C        // Vertical Sync Counter Level MSB
#define _VSYNC_COUNTER_LEVEL_LSB_4D 			0x4D        // Vertical Sync Counter Level LSB
#define _HSYNC_TYPE_DETECTION_FLAG_4E			0x4E        // Hsync Type Detection Flag
#define _STABLE_MEASURE_4F                  	0x4F        // Stable Measure
#define _STABLE_PERIOD_H_50                 	0x50        // Stable Period HByte
#define _STABLE_PERIOD_L_51                 	0x51        // Stable Period LByte
#define _MEAS_HS_PERIOD_H_52               		0x52        // HSync Period Measured Result HByte
#define _MEAS_HS_PERIOD_L_53                	0x53        // HSync Period Measured Result LByte
#define _MEAS_VS_PERIOD_H_54                	0x54        // VSync Period Measured Result HByte
#define _MEAS_VS_PERIOD_L_55                	0x55        // VSync Period Measured Result LByte
#define _MEAS_HS_VS_HIGH_PERIOD_H_56			0x56        // HSync and VSync High Period Measured Results HByte
#define _MEAS_HS_HIGH_PERIOD_L_57       		0x57        // HSync High Period Measured Results LByte
#if(_SCALER_TYPE == _RTD3580D)
#define _MEAS_HS_VS_HI_SEL_58               	0x58        // HSync and VSync High Period Measured Select
#else
#define _MEAS_VS_HIGH_PERIOD_L_58       		0x58        // VSync High Period Measured Results LByte
#endif
#define _MEAS_ACTIVE_REGION_59              	0x59        // Active Region Measured by Crystal Clock
//#define _SYNC_TEST_MISC_5A                  	0x5A        // Sync Test MISC Register
//Address: 5B Reserved
#define _SYNC_PROC_ACCESS_PORT_5C     			0x5C        // Sync Processor Access Port Address
#define _SYNC_PROC_DATA_PORT_5D          		0x5D        // Sync Processor Access Port Data
//Address: 5E~5F Reserved

//--------------------------------------------------
// Hightlight Window(Port)
//--------------------------------------------------
#define _HW_ACCESS_PORT_60                  	0x60        // Highlight Window Access Port
#define _HW_DATA_PORT_61                    	0x61        // Highlight Window Data Port

//--------------------------------------------------
// Color Processor Control(Port)
//--------------------------------------------------
#define _COLOR_CTRL_62                      	0x62        // Color Processor Control Register
#define _SRGB_ACCESS_PORT_63                	0x63        // sRGB Access Port
#define _CB_ACCESS_PORT_64                  	0x64        // Contrast/Brightness Access Port
#define _CB_DATA_PORT_65                    	0x65        // Contrast/Brightness Data Port

//--------------------------------------------------
// Gamma Control
//--------------------------------------------------
#define _GAMMA_PORT_66                      	0x66        // Gamma Access Port
#define _GAMMA_CTRL_67                      	0x67        // Gamma Control Register
#define _GAMMA_BIST_68                      	0x68        // Gamma BIST Control Register

#if(_SCALER_TYPE == _RTD3580D)
//--------------------------------------------------
// Dithering Control
//--------------------------------------------------
#define _DITHERING_DATA_ACCESS_69          		0x69        // Dithering Table DATA ACCESS
#define _DITHERING_CTRL_6A                 		0x6A        // Dithering Control Register
//#define _RESERVED_6B                        		0x6B        // Reserved 6B
#else
//--------------------------------------------------
// Dithering Control
//--------------------------------------------------
#define _DITHERING_SEQUENCE_TABLE_69        	0x69        // Dithering Sequence Table
#define _DITHERING_TABLE_ACCESS_PORT_6A 		0x6A        // Dithering Table Access Port
#define _DITHERING_CTRL_6B                  	0x6B        // Dithering Control Register