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📄 mst705Ȧ

📁 MST705源代码
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12 
		MCUXFR_48_SSPI_TRIG=0xF8;
		MCUXFR_40_SSPI_WD0=0x20; //  Sector Erase 0x00e000
		MCUXFR_41_SSPI_WD1=0;
		MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		MCUXFR_43_SSPI_WD3=0;
		MCUXFR_48_SSPI_TRIG=0xFB;
		Delay1ms(20);

		// WREN + Write Byte
		for (i=0;i<sizeof(g_VideoSetting);i++)
		{
			MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
			MCUXFR_48_SSPI_TRIG=0xF8;
			MCUXFR_40_SSPI_WD0=0x02;  //FlashWriteByte  SST
		    MCUXFR_41_SSPI_WD1=0;
		    MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		    MCUXFR_43_SSPI_WD3=i;
			MCUXFR_44_SSPI_WD4=*(&g_VideoSetting.ucVersion+i);
			MCUXFR_48_SSPI_TRIG=0xFC;
			Delay1ms(10);
		}

		//  Write Protect
		MCUXFR_40_SSPI_WD0=0x01;
		MCUXFR_41_SSPI_WD1=0x0C;
		MCUXFR_48_SSPI_TRIG=0xF9;
	}	
    else if(ChipId==FlashEonF10)
	{
		MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
		MCUXFR_48_SSPI_TRIG=0xf8;

		// Write Status 0x00
		MCUXFR_40_SSPI_WD0=0x01;
        MCUXFR_41_SSPI_WD1=0x94;//0x00;		//protect  0-120K sectors
		MCUXFR_48_SSPI_TRIG=0xF9;

		// Write Enable WREN + Sector Erase
		MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
		MCUXFR_48_SSPI_TRIG=0xF8;
		MCUXFR_40_SSPI_WD0=0x20;//0xD8; //  Sector Erase 0x00e000
		MCUXFR_41_SSPI_WD1=0;
		MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		MCUXFR_43_SSPI_WD3=0;
		MCUXFR_48_SSPI_TRIG=0xFB;
		Delay1ms(10);

		// WREN + Write Byte
		for (i=0;i<sizeof(g_VideoSetting);i++)
		{
			MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
			MCUXFR_48_SSPI_TRIG=0xF8;
			MCUXFR_40_SSPI_WD0=0x02;  //FlashWriteByte  SST
		    MCUXFR_41_SSPI_WD1=0;
		    MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		    MCUXFR_43_SSPI_WD3=i;
			MCUXFR_44_SSPI_WD4=*(&g_VideoSetting.ucVersion+i);
			MCUXFR_48_SSPI_TRIG=0xFC;
			Delay1ms(10);
		}

		//  Write Protect
		MCUXFR_40_SSPI_WD0=0x01;
		MCUXFR_41_SSPI_WD1=0x9C;	//protect all sectors
		MCUXFR_48_SSPI_TRIG=0xF9;
	}	
	else if(ChipId==FlashKH) // KH25L1005
	{
		MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
		MCUXFR_48_SSPI_TRIG=0xf8;

		// Write Status 0x00
		MCUXFR_40_SSPI_WD0=0x01;
		MCUXFR_41_SSPI_WD1=0x00;
		MCUXFR_48_SSPI_TRIG=0xF9;

		// Write Enable WREN + Sector Erase
		MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
		MCUXFR_48_SSPI_TRIG=0xF8;
		MCUXFR_40_SSPI_WD0=0x20; //  Sector Erase 0x00e000
		MCUXFR_41_SSPI_WD1=0;
		MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		MCUXFR_43_SSPI_WD3=0;
		MCUXFR_48_SSPI_TRIG=0xFB;
		Delay1ms(10);

		// WREN + Write Byte
		for (i=0;i<sizeof(g_VideoSetting);i++)
		{
			MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
			MCUXFR_48_SSPI_TRIG=0xF8;
			MCUXFR_40_SSPI_WD0=0x02;  //FlashWriteByte  SST
		    MCUXFR_41_SSPI_WD1=0;
		    MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		    MCUXFR_43_SSPI_WD3=i;
			MCUXFR_44_SSPI_WD4=*(&g_VideoSetting.ucVersion+i);
			MCUXFR_48_SSPI_TRIG=0xFC;
			Delay1ms(10);
		}

		//  Write Protect
		MCUXFR_40_SSPI_WD0=0x01;
		MCUXFR_41_SSPI_WD1=0x84;
		MCUXFR_48_SSPI_TRIG=0xF9;
	}	
	else if(ChipId==FlashAMIC) // A25L512
	{
		MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
		MCUXFR_48_SSPI_TRIG=0xf8;

		// Write Status 0x00
		MCUXFR_40_SSPI_WD0=0x01;
		MCUXFR_41_SSPI_WD1=0x00;
		MCUXFR_48_SSPI_TRIG=0xF9;

		// Write Enable WREN + Sector Erase
		MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
		MCUXFR_48_SSPI_TRIG=0xF8;
		MCUXFR_40_SSPI_WD0=0x20; //  Sector Erase 0x00e000
		MCUXFR_41_SSPI_WD1=0;
		MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		MCUXFR_43_SSPI_WD3=0;
		MCUXFR_48_SSPI_TRIG=0xFB;
		Delay1ms(10);

		// WREN + Write Byte
		for (i=0;i<sizeof(g_VideoSetting);i++)
		{
			MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
			MCUXFR_48_SSPI_TRIG=0xF8;
			MCUXFR_40_SSPI_WD0=0x02;  //FlashWriteByte  SST
		    MCUXFR_41_SSPI_WD1=0;
		    MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		    MCUXFR_43_SSPI_WD3=i;
			MCUXFR_44_SSPI_WD4=*(&g_VideoSetting.ucVersion+i);
			MCUXFR_48_SSPI_TRIG=0xFC;
			Delay1ms(10);
		}

		//  Write Protect
		MCUXFR_40_SSPI_WD0=0x01;
		MCUXFR_41_SSPI_WD1=0x8C;
		MCUXFR_48_SSPI_TRIG=0xF9;
	}	
	else if(ChipId==FlashSaiFun) // SAIFUN flash
	{
		MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
		MCUXFR_48_SSPI_TRIG=0xf8;

		// Write Status 0x00
		MCUXFR_40_SSPI_WD0=0x01;
		MCUXFR_41_SSPI_WD1=0x00;
		MCUXFR_48_SSPI_TRIG=0xF9;

		// Write Enable WREN + Sector Erase
		MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
		MCUXFR_48_SSPI_TRIG=0xF8;
		MCUXFR_40_SSPI_WD0=0x81; //  Sector Erase 0x00e000
		MCUXFR_41_SSPI_WD1=0;
		MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		MCUXFR_43_SSPI_WD3=0;
		MCUXFR_48_SSPI_TRIG=0xFb;
		Delay1ms(6);

		// WREN + Write Byte
		for (i=0;i<sizeof(g_VideoSetting);i++)
		{
			MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
			MCUXFR_48_SSPI_TRIG=0xF8;
			MCUXFR_40_SSPI_WD0=0x02;  //FlashWriteByte  SST
		    MCUXFR_41_SSPI_WD1=0;
		    MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		    MCUXFR_43_SSPI_WD3=i;
			MCUXFR_44_SSPI_WD4=*(&g_VideoSetting.ucVersion+i);
			MCUXFR_48_SSPI_TRIG=0xFC;
			Delay1ms(10);
		}

		//  Write Protect
		MCUXFR_40_SSPI_WD0=0x01;
		MCUXFR_41_SSPI_WD1=0x0C;
		MCUXFR_48_SSPI_TRIG=0xF9;
	}
	else if(ChipId==FlashSST) // SST flash
	{
		MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
		MCUXFR_48_SSPI_TRIG=0xc1;

		// disable Write Protect
		MCUXFR_40_SSPI_WD0=0x50;
		MCUXFR_41_SSPI_WD1=0x01;
		MCUXFR_42_SSPI_WD2=0x00;
		MCUXFR_48_SSPI_TRIG=0xc8;

		// Write Enable WREN + Sector Erase
		MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
		MCUXFR_48_SSPI_TRIG=0xc1;
		MCUXFR_40_SSPI_WD0=0x20; //  Sector Erase 0x00e000
		MCUXFR_41_SSPI_WD1=0;
		MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		MCUXFR_43_SSPI_WD3=0;
		MCUXFR_48_SSPI_TRIG=0xc4;
		Delay1ms(25);  //from spec page 19
		// WREN + Write Byte
		for (i=0;i<sizeof(g_VideoSetting);i++)
		{
			MCUXFR_40_SSPI_WD0=0x06;  // Write Enable WREN
			MCUXFR_48_SSPI_TRIG=0xc1;
			MCUXFR_40_SSPI_WD0=0x02;  //FlashWriteByte  SST
		    MCUXFR_41_SSPI_WD1=0;
		    MCUXFR_42_SSPI_WD2=(BYTE)(address>>8);
		    MCUXFR_43_SSPI_WD3=i;
			MCUXFR_44_SSPI_WD4=*(&g_VideoSetting.ucVersion+i);
			MCUXFR_48_SSPI_TRIG=0xc5;
			Delay1ms(5);
		}

		// Enable Write Protect
		MCUXFR_40_SSPI_WD0=0x50;
		MCUXFR_41_SSPI_WD1=0x01;
		MCUXFR_42_SSPI_WD2=0x0c;
		MCUXFR_48_SSPI_TRIG=0xc8;
    }
}


void mstSaveDisplayData(WORD address)
{
    mstSaveDisplayDataBanked(address);
    Delay1ms(100);
    mstSaveDisplayDataBanked(address+0x1000);
}


void mstLoadDisplayData(WORD address)
{
	BYTE i;
	BYTE code *add;
	add = address;

	WatchDogClear();
	//printf("\r\nRD<%x>",address);

	for (i=0 ; i< sizeof(g_VideoSetting); i++)
	{
		*(&g_VideoSetting.ucVersion+ i) = *(add+i);
	}

}

void NVRam_WriteByte(WORD addr, BYTE value)
{
	 addr=addr;
	 value=value;
	 mstSaveDisplayData(SFD_ADDRESS);
}

void NVRam_WriteTbl(WORD addr, BYTE *buffer, WORD count)
{
	 addr=addr;
	 buffer=buffer;
	 count=count;
	 mstSaveDisplayData(SFD_ADDRESS);
}
// some empty function for RM_EEPROM_TYPE>=RM_TYPE_SST512
void NVRam_WriteWord(WORD addr, WORD value)
{
	 addr=addr;
	 value=value;
	// mstSaveDisplayData(SFD_ADDRESS);
}

void NVRam_ReadTbl(WORD addr, BYTE *buffer, WORD count)
{
        addr=addr;
	 buffer=buffer;
	 count=count;
        //mstLoadDisplayData(SFD_ADDRESS);
}

void NVRam_ReadByte(WORD addr, BYTE *value)
{
	 addr=addr;
	 value=value;
}
#endif
12

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