📄 mst705Ȧ
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//input mux
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,_BIT14,_BIT14);
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,_BIT12,_BIT13|_BIT12);//Set input channel
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,0,0x00FC);
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,1,_BIT1|_BIT0);
msWrite2BytesMask_16bitADDR(BK6s00_03h_ADC_ATOP,_BIT6|_BIT4|_BIT1|_BIT0,_BIT6|_BIT4|_BIT1|_BIT0);
msWrite2BytesMask_16bitADDR(BK6s00_04h_ADC_ATOP,0/*0x0968*/,0xffff);
msWrite2BytesMask_16bitADDR(BK6s00_05h_ADC_ATOP,0x0,0xffff);
//Clock Setup
msWrite2BytesMask_16bitADDR(BK6s00_06h_ADC_ATOP,0x0680,0x07FF);
msWrite2BytesMask_16bitADDR(BK6s00_45h_ADC_ATOP,0x0,_BIT1|_BIT0);
msWrite2BytesMask_16bitADDR(BK6s00_39h_ADC_ATOP,0x0,_BIT12);
msWrite2BytesMask_16bitADDR(BK6s00_22h_ADC_ATOP,0x30,0x00FF);
//CVBS active filter
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,0,0x000F);
//Vclamp
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,0,_BIT8);
//SOG
//msWrite2BytesMask_16bitADDR(BK6s00_29h_ADC_ATOP,_BIT13,_BIT13);Triggle Cal
msWrite2BytesMask_16bitADDR(BK6s00_2Bh_ADC_ATOP,_BIT5/*0x20*/,0x003F);
msWrite2BytesMask_16bitADDR(BK6s00_2Ah_ADC_ATOP,1,_BIT3|_BIT2|_BIT1|_BIT0);//Sel SOG0
msWrite2BytesMask_16bitADDR(BK6s00_2Bh_ADC_ATOP,0,_BIT11|_BIT10);
msWrite2BytesMask_16bitADDR(BK6s00_2Ch_ADC_ATOP,0,_BIT0);
//HSYNC,VSYNC
msWrite2BytesMask_16bitADDR(BK6s00_20h_ADC_ATOP,0,_BIT1|_BIT0);
msWrite2BytesMask_16bitADDR(BK6s00_20h_ADC_ATOP,0,_BIT2|_BIT1|_BIT0);
//PLL setup
msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
msWrite2BytesMask_16bitADDR(BK6s01_01h_ADC_DTOP,0x0800,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_07h_ADC_DTOP,_BIT6|_BIT5,_BIT7|_BIT6|_BIT5);
//Auto phase
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
msWrite2BytesMask_16bitADDR(BK6s00_11h_ADC_ATOP,_BIT10,_BIT10);
msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
msWrite2BytesMask_16bitADDR(BK6s01_5Ch_ADC_DTOP,0,_BIT2);
msWrite2BytesMask_16bitADDR(BK6s01_44h_ADC_DTOP,_BIT14/*4*/,_BIT14|_BIT13|_BIT12);
msWrite2BytesMask_16bitADDR(BK6s01_47h_ADC_DTOP,_BIT14/*4*/,_BIT14|_BIT13|_BIT12);
msWrite2BytesMask_16bitADDR(BK6s01_4Ah_ADC_DTOP,_BIT14/*4*/,_BIT14|_BIT13|_BIT12);
//PGA Gain
msWrite2BytesMask_16bitADDR(BK6s01_5Ah_ADC_DTOP,0x444,0x0FFF);
//Clamp setup
//vclamp
msWrite2BytesMask_16bitADDR(BK6s01_0Dh_ADC_DTOP,_BIT12,_BIT12);
msWrite2BytesMask_16bitADDR(BK6s01_07h_ADC_DTOP,0,0x0018);
msWrite2BytesMask_16bitADDR(BK6s01_0Dh_ADC_DTOP,1,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_08h_ADC_DTOP,_BIT12/*0x10*/,0xFF00);
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,0,_BIT12|_BIT11|_BIT10|_BIT9);
//Vclamp
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,0,_BIT8);
//iclamp
msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
msWrite2BytesMask_16bitADDR(BK6s01_18h_ADC_DTOP,_BIT10|_BIT9|_BIT8/*7*/,_BIT10|_BIT9|_BIT8);//clear bit10 for up of screen flick
msWrite2BytesMask_16bitADDR(BK6s01_19h_ADC_DTOP,0,_BIT12|_BIT11|_BIT10|_BIT9);
//iclamp_r
msWrite2BytesMask_16bitADDR(BK6s01_1Bh_ADC_DTOP,0x0800,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_1Ch_ADC_DTOP,5,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_1Dh_ADC_DTOP,0x07D0,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_1Eh_ADC_DTOP,0x40/*0x60*/,0x007F);
msWrite2BytesMask_16bitADDR(BK6s01_1Eh_ADC_DTOP,_BIT9,0x3F80);
msWrite2BytesMask_16bitADDR(BK6s01_1Fh_ADC_DTOP,_BIT9|_BIT8|_BIT7|_BIT5,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_20h_ADC_DTOP,_BIT12|_BIT11|_BIT10,0x3FFF);
msWrite2BytesMask_16bitADDR(BK6s01_21h_ADC_DTOP,0x540,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_22h_ADC_DTOP,_BIT11|_BIT6|_BIT3|_BIT1,0xFFFF);
msWrite2BytesMask_16bitADDR(BK6s01_23h_ADC_DTOP,_BIT8,0x03FF);
//iclamp_g
msWrite2BytesMask_16bitADDR(BK6s01_26h_ADC_DTOP,0x0080,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_27h_ADC_DTOP,5,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_28h_ADC_DTOP,0x07D0,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_29h_ADC_DTOP,0x40/*0x60*/,0x007F);
msWrite2BytesMask_16bitADDR(BK6s01_29h_ADC_DTOP,_BIT9,0x3F80);
msWrite2BytesMask_16bitADDR(BK6s01_2Ah_ADC_DTOP,_BIT9|_BIT8|_BIT7|_BIT5,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_2Bh_ADC_DTOP,_BIT12|_BIT11|_BIT10,0x3FFF);
msWrite2BytesMask_16bitADDR(BK6s01_2Ch_ADC_DTOP,0x540,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_2Dh_ADC_DTOP,_BIT11|_BIT6|_BIT3|_BIT1,0xFFFF);
msWrite2BytesMask_16bitADDR(BK6s01_2Eh_ADC_DTOP,_BIT8,0x03FF);
//iclamp_b
msWrite2BytesMask_16bitADDR(BK6s01_30h_ADC_DTOP,0x0800,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_31h_ADC_DTOP,5,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_32h_ADC_DTOP,0x07D0,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_33h_ADC_DTOP,0x40/*0x60*/,0x007F);
msWrite2BytesMask_16bitADDR(BK6s01_33h_ADC_DTOP,_BIT9,0x3F80);
msWrite2BytesMask_16bitADDR(BK6s01_34h_ADC_DTOP,_BIT9|_BIT8|_BIT7|_BIT5,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_35h_ADC_DTOP,_BIT12|_BIT11|_BIT10,0x3FFF);
msWrite2BytesMask_16bitADDR(BK6s01_36h_ADC_DTOP,0x540,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_37h_ADC_DTOP,_BIT11|_BIT6|_BIT3|_BIT1,0xFFFF);
msWrite2BytesMask_16bitADDR(BK6s01_38h_ADC_DTOP,_BIT8,0x03FF);
//gain offset setup
msWrite2BytesMask_16bitADDR(BK6s01_51h_ADC_DTOP,0x0740,0x0740);
//adcr gain offset
msWrite2BytesMask_16bitADDR(BK6s01_44h_ADC_DTOP,0x0800,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_46h_ADC_DTOP,0x800,0x7FFF);
//adcg gain offset
msWrite2BytesMask_16bitADDR(BK6s01_47h_ADC_DTOP,0x0080,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_49h_ADC_DTOP,0x100,0x7FFF);
//adcb gain offset
msWrite2BytesMask_16bitADDR(BK6s01_4Ah_ADC_DTOP,0x0800,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_4Ch_ADC_DTOP,0x800,0x7FFF);
msWriteByte( BK0_00_REGBK, REG_BANK7_CHIPTOP );
msWrite2BytesMask_16bitADDR(BK7_22h_CHIPTOP,_BIT3,_BIT3|_BIT2);
break;
case SRCTYPE_VGA:
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
//input mux setup
msWrite2BytesMask_16bitADDR(BK6s00_01h_ADC_ATOP,_BIT0,_BIT2|_BIT1|_BIT0);
//input mux
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,_BIT14,_BIT14);
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,0,_BIT13|_BIT12);//Set input channel
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,0,0x00FC);
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,0,_BIT1|_BIT0);
msWrite2BytesMask_16bitADDR(BK6s00_03h_ADC_ATOP,0,_BIT12|_BIT11|_BIT9|_BIT8);
//Clock Setup
msWrite2BytesMask_16bitADDR(BK6s00_06h_ADC_ATOP,0x0680,0x07FF);
msWrite2BytesMask_16bitADDR(BK6s00_45h_ADC_ATOP,0x0,_BIT1|_BIT0);
msWrite2BytesMask_16bitADDR(BK6s00_39h_ADC_ATOP,0x0,_BIT12);
msWrite2BytesMask_16bitADDR(BK6s00_22h_ADC_ATOP,0x30,0x00FF);
//CVBS active filter
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,0,0x000F);
//Vclamp
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,0,_BIT8);
//SOG
//msWrite2BytesMask_16bitADDR(BK6s00_29h_ADC_ATOP,_BIT13,_BIT13);
msWrite2BytesMask_16bitADDR(BK6s00_2Bh_ADC_ATOP,_BIT5/*0x20*/,0x003F);
msWrite2BytesMask_16bitADDR(BK6s00_2Bh_ADC_ATOP,0,_BIT11|_BIT10);
msWrite2BytesMask_16bitADDR(BK6s00_2Ch_ADC_ATOP,0,_BIT0);
//HSYNC,VSYNC
msWrite2BytesMask_16bitADDR(BK6s00_20h_ADC_ATOP,0,_BIT1|_BIT0);
msWrite2BytesMask_16bitADDR(BK6s00_20h_ADC_ATOP,0,_BIT2|_BIT1|_BIT0);
//ATOP_34[12:10] = 3ˇh100 // For ADC current change to 22mA
msWrite2BytesMask_16bitADDR(BK6s00_34h_ADC_ATOP,_BIT12,_BIT12|_BIT11|_BIT10);
//PLL setup
msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
msWrite2BytesMask_16bitADDR(BK6s01_01h_ADC_DTOP,0x0800,0x1FFF);
#if SOG_ENABLE
msWrite2BytesMask_16bitADDR(BK6s01_07h_ADC_DTOP,_BIT6|_BIT5,_BIT6|_BIT5);
#else
msWrite2BytesMask_16bitADDR(BK6s01_07h_ADC_DTOP,_BIT5,_BIT6|_BIT5);
#endif
//Auto phase
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
msWrite2BytesMask_16bitADDR(BK6s00_11h_ADC_ATOP,_BIT10,_BIT10);
msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
msWrite2BytesMask_16bitADDR(BK6s01_5Ch_ADC_DTOP,0,_BIT2);
msWrite2BytesMask_16bitADDR(BK6s01_44h_ADC_DTOP,_BIT14/*4*/,_BIT14|_BIT13|_BIT12);
msWrite2BytesMask_16bitADDR(BK6s01_47h_ADC_DTOP,_BIT14/*4*/,_BIT14|_BIT13|_BIT12);
msWrite2BytesMask_16bitADDR(BK6s01_4Ah_ADC_DTOP,_BIT14/*4*/,_BIT14|_BIT13|_BIT12);
//PGA Gain
msWrite2BytesMask_16bitADDR(BK6s01_5Ah_ADC_DTOP,0x444,0x0FFF);
//msWrite2BytesMask_16bitADDR(BK6s01_5Ah_ADC_DTOP,0x666,0x0FFF);
//Clamp setup
//vclamp
msWrite2BytesMask_16bitADDR(BK6s01_0Dh_ADC_DTOP,_BIT12,_BIT12);
msWrite2BytesMask_16bitADDR(BK6s01_07h_ADC_DTOP,0,0x0018);
msWrite2BytesMask_16bitADDR(BK6s01_0Dh_ADC_DTOP,1,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_08h_ADC_DTOP,_BIT12/*0x10*/,0xFF00);
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,0,_BIT12|_BIT11|_BIT10|_BIT9);
//Vclamp
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,0,_BIT8);
//iclamp
msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
msWrite2BytesMask_16bitADDR(BK6s01_18h_ADC_DTOP,_BIT10|_BIT9|_BIT8/*7*/,_BIT10|_BIT9|_BIT8);
msWrite2BytesMask_16bitADDR(BK6s01_19h_ADC_DTOP,0,_BIT12|_BIT11|_BIT10|_BIT9);
//iclamp_r
msWrite2BytesMask_16bitADDR(BK6s01_1Bh_ADC_DTOP,0x0080,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_1Ch_ADC_DTOP,5,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_1Dh_ADC_DTOP,0x07D0,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_1Eh_ADC_DTOP,0x40/*0x60*/,0x007F);
msWrite2BytesMask_16bitADDR(BK6s01_1Eh_ADC_DTOP,_BIT9,0x3F80);
msWrite2BytesMask_16bitADDR(BK6s01_1Fh_ADC_DTOP,_BIT9|_BIT8|_BIT7|_BIT5,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_20h_ADC_DTOP,_BIT12|_BIT11|_BIT10,0x3FFF);
msWrite2BytesMask_16bitADDR(BK6s01_21h_ADC_DTOP,0x540,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_22h_ADC_DTOP,_BIT11|_BIT6|_BIT3|_BIT1,0xFFFF);
msWrite2BytesMask_16bitADDR(BK6s01_23h_ADC_DTOP,_BIT8,0x03FF);
//iclamp_g
msWrite2BytesMask_16bitADDR(BK6s01_26h_ADC_DTOP,0x0080,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_27h_ADC_DTOP,5,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_28h_ADC_DTOP,0x07D0,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_29h_ADC_DTOP,0x40/*0x60*/,0x007F);
msWrite2BytesMask_16bitADDR(BK6s01_29h_ADC_DTOP,_BIT9,0x3F80);
msWrite2BytesMask_16bitADDR(BK6s01_2Ah_ADC_DTOP,_BIT9|_BIT8|_BIT7|_BIT5,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_2Bh_ADC_DTOP,_BIT12|_BIT11|_BIT10,0x3FFF);
msWrite2BytesMask_16bitADDR(BK6s01_2Ch_ADC_DTOP,0x540,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_2Dh_ADC_DTOP,_BIT11|_BIT6|_BIT3|_BIT1,0xFFFF);
msWrite2BytesMask_16bitADDR(BK6s01_2Eh_ADC_DTOP,_BIT8,0x03FF);
//iclamp_b
msWrite2BytesMask_16bitADDR(BK6s01_30h_ADC_DTOP,0x0080,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_31h_ADC_DTOP,5,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_32h_ADC_DTOP,0x07D0,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_33h_ADC_DTOP,0x40/*0x60*/,0x007F);
msWrite2BytesMask_16bitADDR(BK6s01_33h_ADC_DTOP,_BIT9,0x3F80);
msWrite2BytesMask_16bitADDR(BK6s01_34h_ADC_DTOP,_BIT9|_BIT8|_BIT7|_BIT5,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_35h_ADC_DTOP,_BIT12|_BIT11|_BIT10,0x3FFF);
msWrite2BytesMask_16bitADDR(BK6s01_36h_ADC_DTOP,0x540,0x1FFF);
msWrite2BytesMask_16bitADDR(BK6s01_37h_ADC_DTOP,_BIT11|_BIT6|_BIT3|_BIT1,0xFFFF);
msWrite2BytesMask_16bitADDR(BK6s01_38h_ADC_DTOP,_BIT8,0x03FF);
//gain offset setup
msWrite2BytesMask_16bitADDR(BK6s01_51h_ADC_DTOP,0x0740,0x0740);
//adcr gain offset
msWrite2BytesMask_16bitADDR(BK6s01_44h_ADC_DTOP,0x0080,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_46h_ADC_DTOP,0,0x7FFF);
//adcg gain offset
msWrite2BytesMask_16bitADDR(BK6s01_47h_ADC_DTOP,0x0080,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_49h_ADC_DTOP,0,0x7FFF);
//adcb gain offset
msWrite2BytesMask_16bitADDR(BK6s01_4Ah_ADC_DTOP,0x0080,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_4Ch_ADC_DTOP,0,0x7FFF);
msWriteByte( BK0_00_REGBK, REG_BANK7_CHIPTOP );
msWrite2BytesMask_16bitADDR(BK7_22h_CHIPTOP,_BIT3,_BIT3|_BIT2);
break;
case SRCTYPE_CVBS:
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
//input mux setup
msWrite2BytesMask_16bitADDR(BK6s00_01h_ADC_ATOP,_BIT1,_BIT2|_BIT1|_BIT0);
//input mux
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,0,_BIT14);
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,0,_BIT7|_BIT6);
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,_BIT4,_BIT5|_BIT4);
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,0,_BIT3|_BIT2);
msWrite2BytesMask_16bitADDR(BK6s00_03h_ADC_ATOP,_BIT11+_BIT8/*5*/,_BIT12|_BIT11|_BIT9|_BIT8);
//Clock Setup
msWrite2BytesMask_16bitADDR(BK6s00_06h_ADC_ATOP,0x04D8,0x07FF);
msWrite2BytesMask_16bitADDR(BK6s00_45h_ADC_ATOP,_BIT0,_BIT1|_BIT0);
//msWrite2BytesMask_16bitADDR(BK6s00_39h_ADC_ATOP,0x0,_BIT12);
msWrite2BytesMask_16bitADDR(BK6s00_22h_ADC_ATOP,0x30,0x00FF);
//CVBS active filter
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,1,0x000F);
//Vclamp
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,_BIT8/*1*/,_BIT8);
//SOG
//msWrite2BytesMask_16bitADDR(BK6s00_29h_ADC_ATOP,_BIT13,_BIT13);
//msWrite2BytesMask_16bitADDR(BK6s00_2Ah_ADC_ATOP,0/*1*/,_BIT3|_BIT2|_BIT1|_BIT0);//Sel SOG0
//msWrite2BytesMask_16bitADDR(BK6s00_2Bh_ADC_ATOP,0x20,0x003F);
//msWrite2BytesMask_16bitADDR(BK6s00_2Bh_ADC_ATOP,0,_BIT11|_BIT10);
msWrite2BytesMask_16bitADDR(BK6s00_2Ch_ADC_ATOP,_BIT0,_BIT0);//power down SOG
//HSYNC,VSYNC
msWrite2BytesMask_16bitADDR(BK6s00_20h_ADC_ATOP,0,_BIT2|_BIT1|_BIT0);
//VD PLL
#if ENABLE_VD_32FSC
msWrite2BytesMask_16bitADDR(BK6s00_0Ah_ADC_ATOP,0xC100,0xFF00);
#else//For 8FSC
msWrite2BytesMask_16bitADDR(BK6s00_0Ah_ADC_ATOP,0xB000,0xFF00);
#endif
//ATOP_34[12:10] = 3ˇh100 // For ADC current change to 22mA
msWrite2BytesMask_16bitADDR(BK6s00_34h_ADC_ATOP,_BIT12,_BIT12|_BIT11|_BIT10);
//gain offset setup
msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
msWrite2BytesMask_16bitADDR(BK6s01_51h_ADC_DTOP,0x57,0x007F);
msWrite2BytesMask_16bitADDR(BK6s01_51h_ADC_DTOP,_BIT10|_BIT8,_BIT10|_BIT9|_BIT8);
//adcg gain offset
msWrite2BytesMask_16bitADDR(BK6s01_47h_ADC_DTOP,0x3C0,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_49h_ADC_DTOP,0x3C0,0x7FFF);
msWriteByte( BK0_00_REGBK, REG_BANK7_CHIPTOP );
#if ENABLE_VD_32FSC
msWrite2BytesMask_16bitADDR(BK7_22h_CHIPTOP,0,_BIT3|_BIT2);
#else//For 8FSC
msWrite2BytesMask_16bitADDR(BK7_22h_CHIPTOP,_BIT5|_BIT3|_BIT1,0x003F);
#endif
break;
case SRCTYPE_SVIDEO:
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
//input mux setup
msWrite2BytesMask_16bitADDR(BK6s00_01h_ADC_ATOP,_BIT2|_BIT1/*6*/,_BIT2|_BIT1|_BIT0);
//input mux
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,0,_BIT14);
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,0,_BIT7|_BIT6);
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,_BIT4/*1*/,_BIT5|_BIT4);
msWrite2BytesMask_16bitADDR(BK6s00_02h_ADC_ATOP,_BIT2/*1*/,_BIT3|_BIT2);
msWrite2BytesMask_16bitADDR(BK6s00_03h_ADC_ATOP,_BIT11|_BIT9|_BIT8/*7*/,_BIT12|_BIT11|_BIT9|_BIT8);
//Clock Setup
msWrite2BytesMask_16bitADDR(BK6s00_06h_ADC_ATOP,0x04C8,0x07FF);
msWrite2BytesMask_16bitADDR(BK6s00_45h_ADC_ATOP,0x01,_BIT1|_BIT0);
//msWrite2BytesMask_16bitADDR(BK6s00_39h_ADC_ATOP,0x0,_BIT12);
msWrite2BytesMask_16bitADDR(BK6s00_22h_ADC_ATOP,0x30,0x00FF);
//CVBS active filter
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,3,0x000F);
//ATOP_34[12:10] = 3ˇh100 // For ADC current change to 22mA
msWrite2BytesMask_16bitADDR(BK6s00_34h_ADC_ATOP,_BIT12,_BIT12|_BIT11|_BIT10);
//Vclamp
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,_BIT8/*1*/,_BIT8);
//SOG
//msWrite2BytesMask_16bitADDR(BK6s00_29h_ADC_ATOP,_BIT13/*1*/,_BIT13);
//msWrite2BytesMask_16bitADDR(BK6s00_2Bh_ADC_ATOP,0x20,0x003F);
//msWrite2BytesMask_16bitADDR(BK6s00_2Bh_ADC_ATOP,0,_BIT11|_BIT10);
msWrite2BytesMask_16bitADDR(BK6s00_2Ch_ADC_ATOP,1,_BIT0);//power down SOG
//HSYNC,VSYNC
msWrite2BytesMask_16bitADDR(BK6s00_20h_ADC_ATOP,0,_BIT2|_BIT1|_BIT0);
//VD PLL
#if ENABLE_VD_32FSC
msWrite2BytesMask_16bitADDR(BK6s00_0Ah_ADC_ATOP,0xC100,0xFF00);
#else//For 8FSC
msWrite2BytesMask_16bitADDR(BK6s00_0Ah_ADC_ATOP,0xB000,0xFF00);
#endif
//gain offset setup
msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
msWrite2BytesMask_16bitADDR(BK6s01_51h_ADC_DTOP,0x57,0x007F);
msWrite2BytesMask_16bitADDR(BK6s01_51h_ADC_DTOP,_BIT10|_BIT8,_BIT10|_BIT9|_BIT8);
//adcr gain offset
msWrite2BytesMask_16bitADDR(BK6s01_44h_ADC_DTOP,0x800,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_46h_ADC_DTOP,0x800,0x7FFF);
//adcg gain offset
msWrite2BytesMask_16bitADDR(BK6s01_47h_ADC_DTOP,0x3C0,0x0FFF);
msWrite2BytesMask_16bitADDR(BK6s01_49h_ADC_DTOP,0x3C0,0x7FFF);
msWriteByte( BK0_00_REGBK, REG_BANK7_CHIPTOP );
#if ENABLE_VD_32FSC
msWrite2BytesMask_16bitADDR(BK7_22h_CHIPTOP,0,_BIT3|_BIT2);
#else//For 8FSC
msWrite2BytesMask_16bitADDR(BK7_22h_CHIPTOP,_BIT5|_BIT3|_BIT1,0x003F);
#endif
break;
}
if(SRCTYPE>=SRCTYPE_CVBS)//For CVBS and S-Video
{
//Auto phase
msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
msWrite2BytesMask_16bitADDR(BK6s01_5Ch_ADC_DTOP,_BIT2/*1*/,_BIT2);
msWrite2BytesMask_16bitADDR(BK6s01_44h_ADC_DTOP,_BIT14/*4*/,_BIT14|_BIT13|_BIT12);
msWrite2BytesMask_16bitADDR(BK6s01_47h_ADC_DTOP,_BIT14/*4*/,_BIT14|_BIT13|_BIT12);
msWrite2BytesMask_16bitADDR(BK6s01_4Ah_ADC_DTOP,_BIT14/*4*/,_BIT14|_BIT13|_BIT12);
}
msWriteByte( BK0_00_REGBK, ucBank );
}
void msSetupInputPort(void)
{
SwitchInputPort(g_VideoSetting.InputType);
ChipPowerUpcontrol();
msNLCCurveInit();
#if(VGA_ENABLE||YPBPR_ENABLE)
if( IsAnalogPortInUse())
{
msWriteByte(BK0_00_REGBK, REG_BANK_SCALER);
msWriteByte(BK0_0D_LYL, 0x03);
msWriteByte(BK0_16_INTCTROL, 0x00); // 060815 by jony for VGA
msAdjustPCRGB(0x80, 0x80, 0x80);
msWriteByte(BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU );
msWriteByte( BK1_24, 0x50 );
msWriteByte( BK1_25, 0 ); // FPLL_DIVN => Divide by 1
msWriteByte( BK1_29, 0x18 ); // 20051007
msWriteByte( BK1_2C, 0x00 ); // I clamp
msWriteByte( BK0_00_REGBK, REG_BANK_SCALER);
//msWriteByte( BK0_37, 0 ); // 20051004 Lizst: Disable D-Edge
msWriteByte(BK0_76_COL_MATRIX_CTL, 0x30);
msWriteByte( BK0_83_DELTA_L, 0 );
msWriteByte( BK0_84_DELTA_H, 0 );
if(IsVGAInUse())
{
msLPFCtl(LPF_CTL_TURN_OFF);
NEW_ADCSetting(SRCTYPE_VGA);
#if VGA_ENABLE
msWriteRegsTbl(tProgVGAPort);
#endif
}
else
{
msLPFCtl(LPF_CTL_ANALOG_PORT);
NEW_ADCSetting(SRCTYPE_YCBCR);
#if YPBPR_ENABLE
msWriteRegsTbl(tProgYPbPrPort);
#endif
}
}
else
#endif
{
msWriteByte(BK0_0D_LYL, 0x03);
#if (ENABLE_DDC2BI)
msWriteByte(BK0_16_INTCTROL, 0x01); // 060815 by jony for DDC2BI
#endif
msWriteByte(BK0_10_COCTRL1,COCTRL1_VALUE);
#if (ENABLE_SECAM)
msWriteByte(BK0_00_REGBK, REG_BANK2_VD); //junjian 061205 for SECAM to NTSC
msWriteByte(BK2_19_MVDET_EN, 0xC0);
msWriteByte(BK0_00_REGBK, REG_BANK_SCALER);
#endif
if( IsVideoPortInUse())
{
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