📄 mst705Ȧ
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{
BYTE ucBank = msReadByte( BK0_00_REGBK );
msWriteByte( BK0_00_REGBK, REG_BANK6s02_ADCDTOP2 );
//>>>>>>>>>>>>>>>>>Offset/Gain Mismatch Calibration (one-shot):<<<<<<<<<<<<<<<<<<<<<<//
//Analog PGA = 4ˇh4.......??????
//DTOPB_3F[3:0] = 4ˇhF // Set gain calibration HVREF = 1.05v.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,0x0F,0x000F);
//DTOPB_3F[7:4] = 4ˇhB // Set gain calibration LVREF = 0.55v
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT7|_BIT5|_BIT4/*0x0B*/,0x00F0);
//DTOPB_3F[11:8] = 4ˇh4 // Set analog PGA gain for 0.9V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT10/*0x04*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15,_BIT15);
//DTOPB_40[11:0] = 12'h8E3 // Set R/G/B gain calibration target code. 4095*0.5/0.9 = 2275{12bits}
msWrite2BytesMask_16bitADDR(BK6s02_40h_ADC_DTOP2,0x08E3,0x0FFF);
//DTOPB_41[3:0] = 4ˇh4 // Set R/G/B gain calibration target write.
msWrite2BytesMask_16bitADDR(BK6s02_41h_ADC_DTOP2,4,0x000F);
//DTOPB_41[7] = 1ˇh1 // Write R/G/B gain calibration target code to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_41h_ADC_DTOP2,_BIT7,_BIT7);
//DTOPB_05[3] = 1ˇh1 // select self gain pulse active
msWrite2BytesMask_16bitADDR(BK6s02_05h_ADC_DTOP2,_BIT3,_BIT3);
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
//ATOP_34[0] = 1ˇh1 // Set LDO enable.
msWrite2BytesMask_16bitADDR(BK6s00_34h_ADC_ATOP,_BIT0,_BIT0);
//ATOP_34[3] = 1ˇh1 // Set trim_ldo_selection to TRIM path
msWrite2BytesMask_16bitADDR(BK6s00_34h_ADC_ATOP,_BIT3,_BIT3);
msWriteByte( BK0_00_REGBK, REG_BANK6s02_ADCDTOP2 );
//DTOPB_03[12:11] = 2'h2 // Set offset/gain calibration mode.
msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,_BIT12,_BIT12|_BIT11);
//DTOPB_03[13] = 1'h0 // disable gain calibration cal_all_gain mode.
msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,0,_BIT13);
//DTOPB_7B[15:13] = 3ˇh0 // No need HSYNC/VSYNC pulse for mismatch calibration.
msWrite2BytesMask_16bitADDR(BK6s02_7Bh_ADC_DTOP2,0,_BIT15|_BIT14|_BIT13);
//DTOPB_13[0] = 1ˇh1 // Set offset calibration long mode.
msWrite2BytesMask_16bitADDR(BK6s02_13h_ADC_DTOP2,1,_BIT0);
//DTOPB_13[3:1] = 3ˇh7 // Set RGB offset calibration enable.
msWrite2BytesMask_16bitADDR(BK6s02_13h_ADC_DTOP2,7,0x000F);
//DTOPB_14[11:0] = 12'h03F // Set R/G/B offset calibration delay.
msWrite2BytesMask_16bitADDR(BK6s02_14h_ADC_DTOP2,0x03F,0x0FFF);
//DTOPB_15[7:0] = 8'hFF // Set R/G/B offset calibration duration
msWrite2BytesMask_16bitADDR(BK6s02_15h_ADC_DTOP2,0xFF,0x00FF);
//DTOPB_1F[0] = 1ˇh1 // Set gain calibration long mode.
msWrite2BytesMask_16bitADDR(BK6s02_1Fh_ADC_DTOP2,1,_BIT0);
//DTOPB_1F[3:1] = 3ˇh7 // Set RGB gain calibration enable.
msWrite2BytesMask_16bitADDR(BK6s02_1Fh_ADC_DTOP2,_BIT3|_BIT2|_BIT1,0x000E);
//DTOPB_1F[4] = 1ˇh0 // disable gain mismatch calibration only mode
msWrite2BytesMask_16bitADDR(BK6s02_1Fh_ADC_DTOP2,0,_BIT4);
//DTOPB_20[11:0] = 12'h03F // Set R/G/B gain calibration delay.
msWrite2BytesMask_16bitADDR(BK6s02_20h_ADC_DTOP2,0x03F,0x0FFF);
//DTOPB_21[15:0] = 16'hFFFF// Set R/G/B gain calibration duration.
msWrite2BytesMask_16bitADDR(BK6s02_21h_ADC_DTOP2,0xFFFF,0xFFFF);
//ADCR:
//DTOPB_05[2:0] = 3ˇh6 // Bypass G/B channel.
msWrite2BytesMask_16bitADDR(BK6s02_05h_ADC_DTOP2,_BIT2|_BIT1/*6*/,_BIT2|_BIT1|_BIT0);
//DTOPB_03[8] = 1ˇh1 // Set mismatch calibration start.
msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,_BIT8,_BIT8);
//Wait DTOPB_48[15] = 1ˇh1 // Wait R offset calibration done.
msADCWaitStatusReady(BK6s02_48h_ADC_DTOP2+1,_BIT7);
//Wait DTOPB_4B[15] = 1ˇh1 // Wait R gain calibration done.
msADCWaitStatusReady(BK6s02_4Bh_ADC_DTOP2+1,_BIT7);
//ADCG:
//DTOPB_05[2:0] = 3ˇh5 // Bypass R/B channel.
msWrite2BytesMask_16bitADDR(BK6s02_05h_ADC_DTOP2,_BIT2|_BIT0/*5*/,_BIT2|_BIT1|_BIT0);
//DTOPB_03[8] = 1ˇh1 // Set mismatch calibration start.
msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,_BIT8,_BIT8);
//Wait DTOPB_49[15] = 1ˇh1 // Wait G offset calibration done.
msADCWaitStatusReady(BK6s02_49h_ADC_DTOP2+1,_BIT7);
//Wait DTOPB_4C[15] = 1ˇh1 // Wait G gain calibration done.
msADCWaitStatusReady(BK6s02_4Ch_ADC_DTOP2+1,_BIT7);
//ADCB:
//DTOPB_05[2:0] = 3ˇh3 // Bypass R/G channel.
msWrite2BytesMask_16bitADDR(BK6s02_05h_ADC_DTOP2,_BIT1|_BIT0,_BIT2|_BIT1|_BIT0);
//DTOPB_03[8] = 1ˇh1 // Set mismatch calibration start.
msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,_BIT8,_BIT8);
//Wait DTOPB_4A[15] = 1ˇh1 // Wait B offset calibration done.
msADCWaitStatusReady(BK6s02_4Ah_ADC_DTOP2+1,_BIT7);
//Wait DTOPB_4D[15] = 1ˇh1 // Wait B gain calibration done.
msADCWaitStatusReady(BK6s02_4Dh_ADC_DTOP2+1,_BIT7);
msWriteByte( BK0_00_REGBK, ucBank );
}
#endif//#if (VGA_ENABLE || YPBPR_ENABLE)
#endif
///////////////////////////////////////////////////////////////////////////////
// <Function>: ADCWaitStatusReady
//
// <Description>: Wait for status ready.
//
// <Parameter>: - <Flow> - <Description>
//-----------------------------------------------------------------------------
// ucRegIndex - In - Register index
// ucRegMask - In - Status mask
///////////////////////////////////////////////////////////////////////////////
void msADCWaitStatusReady(BYTE ucRegIndex, BYTE ucRegMask)
{
WORD wDummy = 250; // loop dummy
#if( ENABLE_MCU_USE_INTERNAL_CLOCK )
wDummy = 1000;
#endif
while (!(msReadByte(ucRegIndex) & ucRegMask) && (wDummy--)) ;
}
//////////////////////////////////////////////////////////////////////
// A. ADC_B (G ADC is used for CVBS Y) Self Mismatch Calibration:
// After VD clock is set,
// we start to calibrate differential ADC linear/offset/gain mismatched.
//////////////////////////////////////////////////////////////////////
void msADCSelfMismatchCal_CVBS_SVIDEO_Y(void)
{
BYTE ucBank = msReadByte( BK0_00_REGBK );
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
//ATOP_28[8] = 1'b0 // Set VCLP equal to 0.8V
msWrite2BytesMask_16bitADDR(BK6s00_28h_ADC_ATOP,0,_BIT8);
msWriteByte( BK0_00_REGBK, REG_BANK6s02_ADCDTOP2 );
//>>>>>>>>>>>>>>>>>Linear Mismatch Calibration:<<<<<<<<<<<<<<<<<<<<<<//
//ADCG:
//DTOPB_03[12:11] = 2'h1 // Set linear calibration mode only.
msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,_BIT11/*1*/,_BIT12|_BIT11);
//DTOPB_7B[15:13] = 3ˇh0 // No need HSYNC/VSYNC pulse for mismatch calibration.
msWrite2BytesMask_16bitADDR(BK6s02_7Bh_ADC_DTOP2,0,_BIT15|_BIT14|_BIT13);
//DTOPB_07[0] = 1ˇb1 // Set linear calibration long mode.
msWrite2BytesMask_16bitADDR(BK6s02_07h_ADC_DTOP2,1,_BIT0);
//DTOPB_07[11:8] = 4ˇhE // Set analog PGA gain in linear calibration mode.
msWrite2BytesMask_16bitADDR(BK6s02_07h_ADC_DTOP2,0x0E00,0x0F00);
//DTOPB_07[15:12] = 4ˇhF // Set linear calibration reference voltage in 1.05v
msWrite2BytesMask_16bitADDR(BK6s02_07h_ADC_DTOP2,0xF000,0xF000);
//DTOPB_08[2:0] = 3ˇh7 // Set RGB linear calibration enable.
msWrite2BytesMask_16bitADDR(BK6s02_08h_ADC_DTOP2,0x07,_BIT2|_BIT1|_BIT0);
//DTOPB_09[11:0] = 12'h03F // Set R/G/B linear calibration delay.
msWrite2BytesMask_16bitADDR(BK6s02_09h_ADC_DTOP2,0x03F,0x0FFF);
//DTOPB_0A[7:0] = 8'hFF // Set R/G/B linear calibration duration
msWrite2BytesMask_16bitADDR(BK6s02_0Ah_ADC_DTOP2,0xFF,0x00FF);
//DTOPB_0B[5] = 1ˇh0 // Set R linear calibration alternative disable.
msWrite2BytesMask_16bitADDR(BK6s02_0Bh_ADC_DTOP2,0,_BIT5);
//DTOPB_0B[13] = 1ˇh0 // Set G linear calibration alternative disable.
msWrite2BytesMask_16bitADDR(BK6s02_0Bh_ADC_DTOP2,0,_BIT13);
//DTOPB_0C[5] = 1ˇh0 // Set B linear calibration alternative disable.
msWrite2BytesMask_16bitADDR(BK6s02_0Ch_ADC_DTOP2,0,_BIT5);
//DTOPB_05[2:0] = 3ˇh5 // Bypass R/B channel.
msWrite2BytesMask_16bitADDR(BK6s02_05h_ADC_DTOP2,5,_BIT2|_BIT1|_BIT0);
//DTOPB_03[8] = 1ˇh1 // Set mismatch calibration start.
msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,_BIT8/*1*/,_BIT8);
//Wait DTOPB_46[15] = 1ˇh1 // Wait G linear calibration done.
msADCWaitStatusReady(BK6s02_46h_ADC_DTOP2+1,_BIT7);
//Offset/Gain Mismatch Calibration:
//DTOPB_05[3] = 1ˇh1 // select self gain pulse active
msWrite2BytesMask_16bitADDR(BK6s02_05h_ADC_DTOP2,_BIT3/*1*/,_BIT3);
msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
//ATOP_34[0] = 1ˇh1 // Set LDO enable.
msWrite2BytesMask_16bitADDR(BK6s00_34h_ADC_ATOP,1,_BIT0);
//ATOP_34[3] = 1ˇh0 // Set trim_ldo_selection to TRIM path
msWrite2BytesMask_16bitADDR(BK6s00_34h_ADC_ATOP,0,_BIT3);
msWriteByte( BK0_00_REGBK, REG_BANK6s02_ADCDTOP2 );
//DTOPB_3F[3:0] = 4ˇhE // Set gain calibration HVREF = 0.90v.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,0x0E,0x000F);
//DTOPB_3F[7:4] = 4ˇhD // Set gain calibration LVREF = 0.65v.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,0x0D0,0x00F0);
//DTOPB_3F[11:8] = 4ˇh0 // Set analog PGA gain for 0.5V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,0x00,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*1*/,_BIT15);
//DTOPB_3F[11:8] = 4ˇh1 // Set analog PGA gain for 0.6V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT8/*1*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*1*/,_BIT15);
//DTOPB_3F[3:0] = 4ˇhF // Set gain calibration HVREF = 1.05v.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,0x0F,0x000F);
//DTOPB_3F[7:4] = 4ˇhB // Set gain calibration LVREF = 0.55v.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,0x0B0,0x00F0);
//DTOPB_3F[11:8] = 4ˇh2 // Set analog PGA gain for 0.7V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT9/*0x02*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*0x01*/,_BIT15);
//DTOPB_3F[11:8] = 4ˇh3 // Set analog PGA gain for 0.8V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT9|_BIT8/*0x03*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*1*/,_BIT15);
//DTOPB_3F[11:8] = 4ˇh4 // Set analog PGA gain for 0.9V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT10/*0x04*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*1*/,_BIT15);
//DTOPB_3F[11:8] = 4ˇh5 // Set analog PGA gain for 1.0V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT10|_BIT8/*0x05*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*1*/,_BIT15);
//DTOPB_3F[11:8] = 4ˇh6 // Set analog PGA gain for 1.1V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT10|_BIT9/*0x06*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*1*/,_BIT15);
//DTOPB_3F[11:8] = 4ˇh7 // Set analog PGA gain for 1.2V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT10|_BIT9|_BIT8/*0x07*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*1*/,_BIT15);
//DTOPB_3F[11:8] = 4ˇh8 // Set analog PGA gain for 1.3V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT11/*0x08*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*1*/,_BIT15);
//DTOPB_3F[11:8] = 4ˇh9 // Set analog PGA gain for 1.4V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT11|_BIT8/*0x09*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*1*/,_BIT15);
//DTOPB_3F[11:8] = 4ˇhA // Set analog PGA gain for 1.5V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT11|_BIT9/*0x0A*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT15/*1*/,_BIT15);
//DTOPB_3F[11:8] = 4ˇhB // Set analog PGA gain for 1.6V input level.
msWrite2BytesMask_16bitADDR(BK6s02_3Fh_ADC_DTOP2,_BIT11|_BIT9|_BIT8/*0x0B*/,0x0F00);
//DTOPB_3F[15] = 1ˇh1 // Write HVREF/LREF to internal registers.
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