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📁 MST705源代码
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//	{ _BIT2,_BIT6,_BIT10, _BIT14, _BIT2,_BIT6,},//16,300MHz,Value=0x04
};
void msADC_inputLPF(BYTE ucPixClk)
{
	BYTE ucLPFIndex,ucBank = msReadByte( BK0_00_REGBK );
	msWriteByte( BK0_00_REGBK, REG_BANK6s00_ADCATOP );
	if(ucPixClk>200)//input >200
		ucLPFIndex = 15;
	else if((ucPixClk<=200)&&(ucPixClk>180))//200>=input >180
		ucLPFIndex = 14;
	else if((ucPixClk<=180)&&(ucPixClk>160))//180>=input >160
		ucLPFIndex = 13;
	else if((ucPixClk<=160)&&(ucPixClk>140))//160>=input >140
		ucLPFIndex = 12;
	else if((ucPixClk<=140)&&(ucPixClk>120))//140>=input >120
		ucLPFIndex = 11;
	else if((ucPixClk<=120)&&(ucPixClk>100))//120>=input >100
		ucLPFIndex = 10;
	else if((ucPixClk<=100)&&(ucPixClk>80))//100>=input >80
		ucLPFIndex = 9;
	else if((ucPixClk<=80)&&(ucPixClk>70))//80>=input >70
		ucLPFIndex = 8;
	else if((ucPixClk<=70)&&(ucPixClk>60))//70>=input >60
		ucLPFIndex = 7;
	else if((ucPixClk<=60)&&(ucPixClk>45))//60>=input >45
		ucLPFIndex = 6;
	else if((ucPixClk<=45)&&(ucPixClk>40))//45>=input >40
		ucLPFIndex = 5;
	else if((ucPixClk<=40)&&(ucPixClk>30))//40>=input >30
		ucLPFIndex = 4;
	else if((ucPixClk<=30)&&(ucPixClk>20))//30>=input >20
		ucLPFIndex = 3;
	else if((ucPixClk<=20)&&(ucPixClk>15))//20>=input >15
		ucLPFIndex = 2;
	else if((ucPixClk<=15)&&(ucPixClk>5))//15>=input >5
		ucLPFIndex = 1;
	else //if(ucPixClk<=5)//5
		ucLPFIndex = 0;
#if VGA_ENABLE
	if(IsVGAInUse())
	{
	msWrite2BytesMask_16bitADDR(BK6s00_24h_ADC_ATOP,tInputLDFTBL_RGB[ucLPFIndex][0],0x000F);//reg_blpf_bwp
	msWrite2BytesMask_16bitADDR(BK6s00_24h_ADC_ATOP,tInputLDFTBL_RGB[ucLPFIndex][1],0x00F0);//reg_blpf_bwm
	msWrite2BytesMask_16bitADDR(BK6s00_24h_ADC_ATOP,tInputLDFTBL_RGB[ucLPFIndex][2],0x0F00);//reg_glpf_bwp
	msWrite2BytesMask_16bitADDR(BK6s00_24h_ADC_ATOP,tInputLDFTBL_RGB[ucLPFIndex][3],0xF000);//reg_glpf_bwm
	msWrite2BytesMask_16bitADDR(BK6s00_25h_ADC_ATOP,tInputLDFTBL_RGB[ucLPFIndex][4],0x000F);//reg_rlpf_bwp
	msWrite2BytesMask_16bitADDR(BK6s00_25h_ADC_ATOP,tInputLDFTBL_RGB[ucLPFIndex][5],0x00F0);//reg_rlpf_bwm
		}
#endif//#if VGA_ENABLE
#if YPBPR_ENABLE
  if (IsYPbPrInUse())
	{
	msWrite2BytesMask_16bitADDR(BK6s00_24h_ADC_ATOP,tInputLDFTBL_YPbPr[ucLPFIndex][0],0x000F);//reg_blpf_bwp
	msWrite2BytesMask_16bitADDR(BK6s00_24h_ADC_ATOP,tInputLDFTBL_YPbPr[ucLPFIndex][1],0x00F0);//reg_blpf_bwm
	msWrite2BytesMask_16bitADDR(BK6s00_24h_ADC_ATOP,tInputLDFTBL_YPbPr[ucLPFIndex][2],0x0F00);//reg_glpf_bwp
	msWrite2BytesMask_16bitADDR(BK6s00_24h_ADC_ATOP,tInputLDFTBL_YPbPr[ucLPFIndex][3],0xF000);//reg_glpf_bwm
	msWrite2BytesMask_16bitADDR(BK6s00_25h_ADC_ATOP,tInputLDFTBL_YPbPr[ucLPFIndex][4],0x000F);//reg_rlpf_bwp
	msWrite2BytesMask_16bitADDR(BK6s00_25h_ADC_ATOP,tInputLDFTBL_YPbPr[ucLPFIndex][5],0x00F0);//reg_rlpf_bwm
		}
#endif//#if YPBPR_ENABLE
	msWriteByte( BK0_00_REGBK, ucBank );
}

//////////////////////////////////////////////////////////////////////
//	depend on pixel clock frequency
//	0x020: < 45MHz
//	0x040: 60~160MHz
//	0x080: > 160MHz
//////////////////////////////////////////////////////////////////////
void msADC_iclamp_clpdur(BYTE ucPixClk)
{
	BYTE ucBank = msReadByte( BK0_00_REGBK );
	msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
	if(ucPixClk>160)//input >160
		msWrite2BytesMask_16bitADDR(BK6s01_18h_ADC_DTOP,0x080,0xFF);
	else if(ucPixClk<45)//input <45MHz
		msWrite2BytesMask_16bitADDR(BK6s01_18h_ADC_DTOP,0x020,0xFF);
	else
		msWrite2BytesMask_16bitADDR(BK6s01_18h_ADC_DTOP,0x040,0xFF);
	msWriteByte( BK0_00_REGBK, ucBank );
}
//////////////////////////////////////////////////////////////////////
//	depend on pixel clock frequency
//	To RGB input
//	0x010: < 30MHz
//	0x020: 20~120MHz
//	0x030: > 120MHz
//	To YPbPr input
//	0x030: < 45MHz
//	0x020: 20~120MHz
//	0x030: > 120MHz
//////////////////////////////////////////////////////////////////////
void msADC_iclamp_clpdly(BYTE ucPixClk)
{
		BYTE ucBank = msReadByte( BK0_00_REGBK );
		msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
#if VGA_ENABLE
		if(IsVGAInUse())
		{
			if(ucPixClk>120)//>120MHz
				msWrite2BytesMask_16bitADDR(BK6s01_17h_ADC_DTOP,0x030,0x0FFF);
			else if(ucPixClk<30)//input <30MHz
				msWrite2BytesMask_16bitADDR(BK6s01_17h_ADC_DTOP,0x010,0x0FFF);
			else
				msWrite2BytesMask_16bitADDR(BK6s01_17h_ADC_DTOP,0x020,0x0FFF);
		}
#endif//#if VGA_ENABLE
#if YPBPR_ENABLE
		if (IsYPbPrInUse())
		{
			if(ucPixClk<45)//input <45MHz
				msWrite2BytesMask_16bitADDR(BK6s01_17h_ADC_DTOP,0x030,0x0FFF);
			else
				msWrite2BytesMask_16bitADDR(BK6s01_17h_ADC_DTOP,0x045,0x0FFF);
    }
#endif//#if YPBPR_ENABLE
	msWriteByte( BK0_00_REGBK, ucBank );
}
//////////////////////////////////////////////////////////////////////
//	depend on pixel clock frequency
//	2'h0: <= 60MHz
//	2'h1: 60~120MHz
//	2'h2: > 120MHz
//////////////////////////////////////////////////////////////////////
void msADC_iclamp_clk_rate(BYTE ucPixClk)
{
	BYTE ucBank = msReadByte( BK0_00_REGBK );
	msWriteByte( BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
	if(ucPixClk>120)//>120MHz
		msWrite2BytesMask_16bitADDR(BK6s01_19h_ADC_DTOP,_BIT14,_BIT14|_BIT13);
	else if(ucPixClk<60)//input <60MHz
		msWrite2BytesMask_16bitADDR(BK6s01_19h_ADC_DTOP,0,_BIT14|_BIT13);
	else //if((ucPixClk<=120)&&(ucPixClk>=60))
			msWrite2BytesMask_16bitADDR(BK6s01_19h_ADC_DTOP,_BIT13,_BIT14|_BIT13);

	msWriteByte( BK0_00_REGBK, ucBank );
}

void msADC_HSYNC_Polarity(BIT bPolarity)
{
    BYTE ucBank = msReadByte(BK0_00_REGBK);
    msWriteByte(BK0_00_REGBK, REG_BANK6s01_ADCDTOP );
    if (bPolarity)
        msWrite2BytesMask_16bitADDR(BK6s01_07h_ADC_DTOP,_BIT7,_BIT7);
    else
        msWrite2BytesMask_16bitADDR(BK6s01_07h_ADC_DTOP,0,_BIT7);
    msWriteByte(BK0_00_REGBK, ucBank );
}

#endif//#if (VGA_ENABLE || YPBPR_ENABLE)
//////////////////////////////////////////////////////////////////////
//	In Maria9 project, we need to do ADC self mismatch calibration to
//	calibrate interleaved ADC mismatch after system power on.
//	Following registers address mapping is used 16-bit mode.
//	The based address of ATOP is Bank_6, Sub Bank 00.
//	The based address of DTOP is Bank_6, Sub Bank 01.
//	The based address of DTOPB is Bank_6, Sub Bank 02.
//////////////////////////////////////////////////////////////////////
#if (VGA_ENABLE || YPBPR_ENABLE)
//////////////////////////////////////////////////////////////////////
//	RGB ADC Self Mismatch Calibration:
//	After
//		(1)	ADC_A free-run clock is set for internal calibration,
//	or
//		(2)	Input mode is detected and ADC_A clock is set,
//	We start to calibrate differential ADC linear/offset/gain mismatched.
//	We do ADC linear calibration firstly.
/////////////////////////////////////////////////////////////////////
void msADCSelfMismatchCal_RGB_YCbCr(void)
{
	BYTE ucBank = msReadByte( BK0_00_REGBK);
	msWriteByte( BK0_00_REGBK, REG_BANK6s02_ADCDTOP2 );
	//>>>>>>>>>>>>>>>>>Linear Mismatch Caliberation(one-shot mode)<<<<<<<<<<<<<<<<<<<<<<//
	//DTOPB_03[12:11] = 2'h1	// Set linear calibration mode only.
	msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,_BIT11,_BIT12|_BIT11);
	//DTOPB_7B[15:13] = 3ˇh0	//No need HSYNC/VSYNC pulse for mismatch calibration.
	msWrite2BytesMask_16bitADDR(BK6s02_7Bh_ADC_DTOP2,0x00,_BIT15|_BIT14|_BIT13);
	//DTOPB_07[0] = 1ˇb1		// Set linear calibration long mode.
	msWrite2BytesMask_16bitADDR(BK6s02_07h_ADC_DTOP2,_BIT0,_BIT0);
	//DTOPB_07[11:8] = 4ˇhE	// Set analog PGA gain in linear calibration mode.
	msWrite2BytesMask_16bitADDR(BK6s02_07h_ADC_DTOP2,_BIT11|_BIT10|_BIT9/*0x0E*/,_BIT11|_BIT10|_BIT9|_BIT8);
	//DTOPB_07[15:12] = 4ˇhF	// Set linear calibration reference voltage in 1.05v
	msWrite2BytesMask_16bitADDR(BK6s02_07h_ADC_DTOP2,_BIT15|_BIT14|_BIT13|_BIT12/*0x0F*/,_BIT15|_BIT14|_BIT13|_BIT12);
	//DTOPB_08[2:0] = 3ˇh7		// Set RGB linear calibration enable.
	msWrite2BytesMask_16bitADDR(BK6s02_08h_ADC_DTOP2,_BIT2|_BIT1|_BIT0/*0x07*/,_BIT2|_BIT1|_BIT0);
	//DTOPB_09[11:0] = 12'h03F	// Set R/G/B linear calibration delay.
	msWrite2BytesMask_16bitADDR(BK6s02_09h_ADC_DTOP2,0x03F,0x0FFF);
	//DTOPB_0A[7:0] = 8'hFF	// Set R/G/B linear calibration duration
	msWrite2BytesMask_16bitADDR(BK6s02_0Ah_ADC_DTOP2,0xFF,0x00FF);
	//DTOPB_0B[5] = 1ˇh0		// Set R linear calibration alternative disable.
	msWrite2BytesMask_16bitADDR(BK6s02_0Bh_ADC_DTOP2,0,_BIT5);
	//DTOPB_0B[13] = 1ˇh0		// Set G linear calibration alternative disable.
	msWrite2BytesMask_16bitADDR(BK6s02_0Bh_ADC_DTOP2,0,_BIT13);
	//DTOPB_0C[5] = 1ˇh0		// Set B linear calibration alternative disable.
	msWrite2BytesMask_16bitADDR(BK6s02_0Ch_ADC_DTOP2,0,_BIT5);

	//ADCR:
	//DTOPB_05[2:0] = 3ˇh6		// Bypass G/B channel.
	msWrite2BytesMask_16bitADDR(BK6s02_05h_ADC_DTOP2,_BIT2|_BIT1/*6*/,_BIT2|_BIT1|_BIT0);
	//DTOPB_03[8] = 1ˇh1		// Set mismatch calibration start. 
	msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,_BIT8,_BIT8);
	//Wait DTOPB_45[15] = 1ˇh1	// Wait R linear calibration done.
	msADCWaitStatusReady(BK6s02_45h_ADC_DTOP2+1,_BIT7);
	//ADCG:
	//DTOPB_05[2:0] = 3ˇh5		// Bypass R/B channel.
	msWrite2BytesMask_16bitADDR(BK6s02_05h_ADC_DTOP2,_BIT2|_BIT0/*5*/,_BIT2|_BIT1|_BIT0);
	//DTOPB_03[8] = 1ˇh1		// Set mismatch calibration start. 
	msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,_BIT8,_BIT8);
	//Wait DTOPB_46[15] = 1ˇh1	// Wait G linear calibration done.
	msADCWaitStatusReady(BK6s02_46h_ADC_DTOP2+1,_BIT7);
	//ADCB:
	//DTOPB_05[2:0] = 3ˇh3		// Bypass R/G channel.
	msWrite2BytesMask_16bitADDR(BK6s02_05h_ADC_DTOP2,_BIT1|_BIT0/*3*/,_BIT2|_BIT1|_BIT0);
	//DTOPB_03[8] = 1ˇh1		// Set mismatch calibration start.
	msWrite2BytesMask_16bitADDR(BK6s02_03h_ADC_DTOP2,_BIT8,_BIT8);
	//Wait DTOPB_47[15] = 1ˇh1	// Wait B linear calibration done.
	msADCWaitStatusReady(BK6s02_47h_ADC_DTOP2+1,_BIT7);
	
	
	msWriteByte( BK0_00_REGBK, ucBank );
}
void msADCGainOffsetMismatchCal_RGB_YCbCr(void)
1234

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