mst705Ȧ

MST705源代码

 {BK0_57_OSCTRL1,0x46},
 {_END_OF_TBL_, 0x00},
};

RegUnitType code tFreeRunModeTbl[]=
{//Reg     Vale
 {BK0_00_REGBK,REG_BANK_SCALER},
 {BK0_27_OPL_SET2, 0x23},
 {BK0_40_VFDEST_L,0x00},
 {BK0_41_VFDEST_H,0x00},
 {BK0_44_VFDEEND_L,0xE9},
 {BK0_50_VSST_L, 0xF2},  // vsync start position
 {BK0_51_VSST_H, 0x0A},
 {_END_OF_TBL_, 0x00},
};

#endif

//*******************************************************************
//Ace setting
#define CbGain	128
#define CrGain	128

#define RedGain		128
#define GreenGain	128
#define BlueGain		128

#define INIT_VIDEO_CONTRAST_X0    60
#define INIT_VIDEO_CONTRAST_X1    70
#define INIT_VIDEO_CONTRAST_X2    110
#define INIT_VIDEO_CONTRAST_X3    130
#define INIT_VIDEO_CONTRAST_X4    140

#define INIT_VIDEO_BRIGHTNESS_X0    0x50
#define INIT_VIDEO_BRIGHTNESS_X1    0x68
#define INIT_VIDEO_BRIGHTNESS_X2    0x80
#define INIT_VIDEO_BRIGHTNESS_X3    0xA0
#define INIT_VIDEO_BRIGHTNESS_X4    0xB0

#define INIT_VIDEO_SATURATION_X0    0
#define INIT_VIDEO_SATURATION_X1    80
#define INIT_VIDEO_SATURATION_X2    140
#define INIT_VIDEO_SATURATION_X3    170
#define INIT_VIDEO_SATURATION_X4    200

#define INIT_SV_CONTRAST_X1    100
#define INIT_SV_CONTRAST_X2    128
#define INIT_SV_CONTRAST_X3    150
#define INIT_SV_CONTRAST_X4    180

#define INIT_SV_BRIGHTNESS_X0    0x50
#define INIT_SV_BRIGHTNESS_X1    0x70
#define INIT_SV_BRIGHTNESS_X2    0x80
#define INIT_SV_BRIGHTNESS_X3    0x90
#define INIT_SV_BRIGHTNESS_X4    0xc0

#define INIT_SV_SATURATION_X0    0
#define INIT_SV_SATURATION_X1    80
#define INIT_SV_SATURATION_X2    168
#define INIT_SV_SATURATION_X3    20
#define INIT_SV_SATURATION_X4    255

#define INIT_VGA_CONTRAST_X0    80
#define INIT_VGA_CONTRAST_X1    100
#define INIT_VGA_CONTRAST_X2    128
#define INIT_VGA_CONTRAST_X3    150
#define INIT_VGA_CONTRAST_X4    180

#define INIT_VGA_BRIGHTNESS_X0    0x50
#define INIT_VGA_BRIGHTNESS_X1    0x70
#define INIT_VGA_BRIGHTNESS_X2    0x80
#define INIT_VGA_BRIGHTNESS_X3    0x90
#define INIT_VGA_BRIGHTNESS_X4    0xc0

#define INIT_YPBPR_CONTRAST_X0    80
#define INIT_YPBPR_CONTRAST_X1    100
#define INIT_YPBPR_CONTRAST_X2    128
#define INIT_YPBPR_CONTRAST_X3    150
#define INIT_YPBPR_CONTRAST_X4    180

#define INIT_YPBPR_BRIGHTNESS_X0    0x40
#define INIT_YPBPR_BRIGHTNESS_X1    0x60
#define INIT_YPBPR_BRIGHTNESS_X2    0x70
#define INIT_YPBPR_BRIGHTNESS_X3    0x90
#define INIT_YPBPR_BRIGHTNESS_X4    0xb0

#define INIT_YPBPR_SATURATION_X0    0
#define INIT_YPBPR_SATURATION_X1    60
#define INIT_YPBPR_SATURATION_X2    128
#define INIT_YPBPR_SATURATION_X3    150
#define INIT_YPBPR_SATURATION_X4    200

#define  INIT_MSVD_COMB_YGAIN        0x90     //BK3_13
#define INIT_MSVD_COMB_CbGAIN       0x96     //BK3_14
#define INIT_MSVD_COMB_CrGAIN        0x6A     //BK3_15
#define INIT_MSVD_COMB_CONTRAST	       0x90  //BK3_63
#define INIT_MSVD_COMB_BRIGHTNESS	0x90  //BK3_64
#define INIT_MSVD_COMB_SATURATION	0x80  //BK3_65
#define INIT_MSVD_TV_BRIGHTNESS	       0x0CE	// bk2_38[6] bk2_3a[7:0] MAXVALUE=0X1FF


#ifdef EnableUseGammaTbl
BYTE code tGammaTableNormal[3][33]=
{
	{
		0x00,0x05,0x0C,0x14,0x1C,0x25,0x2E,0x38,0x41,0x4C,0x56,
		0x60,0x6B,0x75,0x80,0x8A,0x94,0x9E,0xA7,0xB0,0xB9,0xC1,
		0xC8,0xD0,0xD6,0xDD,0xE3,0xE8,0xEE,0xF2,0xF7,0xFB,0xFF,
	},
	{
		0x00,0x05,0x0C,0x14,0x1C,0x25,0x2E,0x38,0x41,0x4C,0x56,
		0x60,0x6B,0x75,0x80,0x8A,0x94,0x9E,0xA7,0xB0,0xB9,0xC1,
		0xC8,0xD0,0xD6,0xDD,0xE3,0xE8,0xEE,0xF2,0xF7,0xFB,0xFF,
	},
	{
		0x00,0x05,0x0C,0x14,0x1C,0x25,0x2E,0x38,0x41,0x4C,0x56,
		0x60,0x6B,0x75,0x80,0x8A,0x94,0x9E,0xA7,0xB0,0xB9,0xC1,
		0xC8,0xD0,0xD6,0xDD,0xE3,0xE8,0xEE,0xF2,0xF7,0xFB,0xFF,
	},
};
#endif

#ifdef EnableColorMatrix
// Smooth ( )
// R Array (0,0), G Array (0,0), B Array (0,0)
// R Adj. (0), G Adj. (0), B Adj. (0)
code short tVideoColorCorrectionMatrix[][3]=
{
   0x03FF, 0x0000, 0x0000, 0x0000, 0x03FF, 0x0000, 0x0000, 0x0000,
   0x03FF,-0x02E6, 0x0288,-0x05BB, 0x07A4,-0x062C, 0x06F3,-0x073C,
  -0x0024, 0x01BF, 0x07EF,-0x0116, 0x01EE, 0x052C,-0x03BB, 0x00B1,
  -0x0831, 0x0000,-0x0000, 0x0000,-0x0000, 0x0000, 0x0000, 0x0000,
};
#endif

#ifdef _EnableFCC_
RegUnitType code tInitializeFCC[] =
{
    /////////////////////////////////////////////////
    // Initialize MACE  table
    /////////////////////////////////////////////////
    {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
    {BK1_56_FCC_CB_1T, 0x70}, // FCC_
    {BK1_57_FCC_CR_1T, 0x9B}, // FCC_
    {BK1_58_FCC_CB_2T, 0x6E}, // FCC_
    {BK1_59_FCC_CR_2T, 0xAC}, // FCC_
    {BK1_5A_FCC_CB_3T, 0xA5}, // FCC_
    {BK1_5B_FCC_CR_3T, 0x69}, // FCC_
    {BK1_5C_FCC_CB_4T, 0x5A}, // FCC_
    {BK1_5D_FCC_CR_4T, 0x9A}, // FCC_
    {BK1_5E_FCC_CB_5T, 0x5A}, // FCC_
    {BK1_5F_FCC_CR_5T, 0x8E}, // FCC_
    {BK1_60_FCC_CB_6T, 0xB0}, // FCC_
    {BK1_61_FCC_CR_6T, 0x48}, // FCC_
    {BK1_62_FCC_CB_7T, 0x64}, // FCC_
    {BK1_63_FCC_CR_7T, 0xC8}, // FCC_
    {BK1_64_FCC_CB_8T, 0x80}, // FCC_
    {BK1_65_FCC_CR_8T, 0x80}, // FCC_
    {BK1_66_FCC_CB_9T, 0x80}, // FCC_
    {BK1_67_FCC_CR_9T, 0xB8},// FCC_
    {BK1_68_FCC_WIN1, 0xA6}, // FCC_
    {BK1_69_FCC_WIN2, 0xBA}, // FCC_
    {BK1_6A_FCC_WIN3, 0xFB}, // FCC_
    {BK1_6B_FCC_WIN4, 0x73}, // FCC_
    {BK1_6C_FCC_WIN5, 0xFB}, // FCC_
    {BK1_6D_FCC_WIN6, 0xFB}, // FCC_
    {BK1_6E_FCC_WIN7, 0xFF}, // FCC_
    {BK1_6F_FCC_WIN8, 0x6A}, // FCC_
    {BK1_70_FCC_WIN9, 0x00}, // FCC_
    {BK1_71_FCC_Y_TH, 0xFF}, // FCC_
    {BK1_72_FCC_K1K2, 0x60}, // FCC_
    {BK1_73_FCC_K3K4, 0x8E}, // FCC_
    {BK1_74_FCC_K5K6, 0x4B}, // FCC_
    {BK1_75_FCC_K7K8, 0x85}, // FCC_
//    {BK1_76_FCC_CTRL, 0x2F}, // FCC_
    //{BK1_77_APP_CTRL, 0x7E}, // FCC_
    {BK1_78_PEAK_BAND1, 0x1D}, // FCC_
    {BK1_79_PEAK_BAND2, 0x50},//0x58}, // FCC_
//    {BK1_7A_LTI, 0x98}, // FCC_
    {BK1_7D_CTI,0x56},//0x78},
    {BK1_7E_VIP_Y_CTRL,0x03},
    {BK1_7F_MAX_PIX, 0x80}, // MAX_PIX
    {BK1_80_MIN_PIX, 0x40}, // MIN_PIX
//    {BK1_81_EGE_BAND1_POS,0x40},
//    {BK1_82_EGE_BAND1_NEG,0x60},
//    {BK1_84_EGE_BAND2_NEG,0x60},
//    {BK1_85_M_BRI,0x04},
//    {BK1_86_EGE_LTI_POS,0x10},
//    {BK1_87_EGE_LTI_NEG,0x20},
//    {BK1_88_YC_LPF,	0x8C},
    {BK1_89, 0x00},
//    {BK1_8A, 0x23},
    {BK1_8B, 0x43},
    {BK1_8C, 0xDF},//0xFF},
    {BK1_8D, 0x9B},//0xAE},
    {BK1_8E, 0x36},
    {BK1_8F, 0x01},

    {BK1_77_APP_CTRL, 0x7E}, // FCC_
    {BK1_85_M_BRI,0x00},

    {BK0_00_REGBK, REG_BANK_SCALER},

    {_END_OF_TBL_, 0x00}
};

RegUnitType code tVideoFCC[] =
{
    {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},

    {BK1_77_APP_CTRL, 0x7E}, // FCC_
    {BK1_85_M_BRI,0x00},
   // {BK1_88_YC_LPF,	0x8C},  //Nelson del

    {BK0_00_REGBK, REG_BANK_SCALER},

    {_END_OF_TBL_, 0x00}
};

#if VGA_ENABLE
RegUnitType code tPCFCC[] =
{
    {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},

    {BK1_77_APP_CTRL, 0}, // FCC_
    {BK1_85_M_BRI,0},
    {BK1_88_YC_LPF,	0},

    {BK0_00_REGBK, REG_BANK_SCALER},

    {_END_OF_TBL_, 0x00}
};
#endif

RegUnitType code t_AVInitializeFCC[] =
{
    {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
    {BK1_76_FCC_CTRL, 0x2F}, // FCC_
    {BK1_7A_LTI, 0x98}, // FCC_
    {BK1_7C_CROING,0x24},//0x42},//0x24},
    {BK1_81_EGE_BAND1_POS,0x40},
    {BK1_82_EGE_BAND1_NEG,0x00},//0x60},
    {BK1_84_EGE_BAND2_NEG,0x30},//0x60},
    {BK1_86_EGE_LTI_POS,0x00},//0x10},
    {BK1_87_EGE_LTI_NEG,0x00},//0x20},
    {BK1_88_YC_LPF,	0x8F},//0x0C},//0x8C},
    {BK1_8A,	0x23},
    {BK0_00_REGBK, REG_BANK_SCALER},

    {_END_OF_TBL_, 0x00},
};

RegUnitType code t_SVInitializeFCC[] =
{
    {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
    {BK1_7A_LTI, 0x08}, // FCC_
    {BK1_7C_CROING,0xFF},
    {BK0_00_REGBK, REG_BANK_SCALER},

    {_END_OF_TBL_, 0x00},
};

RegUnitType code t_TVInitializeFCC[] =
{
    {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
    {BK1_76_FCC_CTRL, 0x2D},
    {BK1_7A_LTI, 0x90},
    {BK1_7C_CROING,0x64},
    {BK1_81_EGE_BAND1_POS,0x00},
    {BK1_82_EGE_BAND1_NEG,0x00},
    {BK1_84_EGE_BAND2_NEG,0x00},
    {BK1_86_EGE_LTI_POS,0x00},
    {BK1_87_EGE_LTI_NEG,0x00},
    {BK1_88_YC_LPF,	0x9C},
    {BK1_8A,	0x43},
    {BK0_00_REGBK, REG_BANK_SCALER},

    {_END_OF_TBL_, 0x00},
};

#endif // _EnableFcc_
#endif