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// for B089AW01
#include "ms_reg.h"
#ifndef _PNL_B089AW01_H_
#define _PNL_B089AW01_H_
#include "devvd.h"
#define PanelName "PanelB089AW01"
#define WidePanel 1
#define PanelDither 8
#define PANEL_TTL 0
#define PANEL_DIGITAL_TCON 0
#define PANEL_ANALOG_TCON 0
#define PANEL_LVDS 1
#define PanelSwapRB 0
#define PanelSwap8BitML 0
#define PanelSwap6BitML 0
#define PanelDClkDelay 0
#define PanelInvDE 0
#define PanelInvDClk 0x8
#define PanelInvHSync 0
#define PanelInvVSync 0
// driving current setting 0==>4mA, 1==>6mA, 2==>8mA ,3==>12mA
#define PanelDCLKCurrent 0 // Dclk current
#define PanelDECurrent 0 // DE signal current
#define PANELHSCURRENT 0 // HSYNC current
#define PANELVSCURRENT 0 // VSYNC current
#define PANELBMCURRENT 0 // B data High-Nibble current
#define PANELBLCURRENT 0 // B data Low-Nibble current
#define PANELGMCURRENT 0 // G data High-Nibble current
#define PANELGLCURRENT 0 // G data Low-Nibble current
#define PANELRMCURRENT 0 // R data High-Nibble current
#define PANELRLCURRENT 0 // R data Low-Nibble current
#define PANELADCLKCURRENT 0 // Analog Panel DCLK current
#if SYSTEM_BOOT_UP_QUICKLY_ENABLE
#define PanelOnTiming1 20//20 // time between panel & data while turn on power
#define PanelOnTiming2 20//20 // time between data & back light while turn on power
#define PanelOffTiming1 2 // time between back light & data while turn off power
#define PanelOffTiming2 2 // time between data & panel while turn off power
#else
#define PanelOnTiming1 200 // time between panel & data while turn on power
#define PanelOnTiming2 200 // time between data & back light while turn on power
#define PanelOffTiming1 20 // time between back light & data while turn off power
#define PanelOffTiming2 20 // time between data & panel while turn off power
#endif
#define PanelHSyncWidth 8//32
#define PanelHSyncBackPorch 16//211
#define PanelVSyncWidth 4
#define PanelVSyncBackPorch 12//24
#define PANEL_DE_VSTART 0
#define PanelHStart (PanelHSyncWidth+PanelHSyncBackPorch)
#define PanelVStart (PanelVSyncWidth+PanelVSyncBackPorch)
#define PanelWidth 1024
#define PanelHeight 600
#define PanelHTotal 1400
#define PanelVTotal 780
#define PanelVdeEnd PanelHeight
#define PanelVSiEnd PanelHeight
#define PanelMinHTotal 1300
#define PanelDCLK (((DWORD)PanelHTotal*PanelVTotal*60)/1000000)
///////////////////////////////////////////////////////
// TCON setting
///////////////////////////////////////////////////////
// PTC Mode setting
#define SET_PTC_MODE1 0x8E // PTC_MODE1(0xD0)
#define SET_PTC_MODE2_NOR 0x3E // BK1_D1_PTC_MODE2(0xD1) ORG:0x18//Tina11282008
#define SET_PTC_MODE2_INV 0x31 // BK1_D1_PTC_MODE2(0xD1) ORG:0x18
#define SET_PTC_MODE3 0x84 // PTC_MODE3(0xD2)
// PTC Timming Setting
#define SET_FRP_TRAN 0x13 // GPO_FRP_TRAN(0xDC)
#define SET_STH_START 0x46 // GPO_STH_START(0xDD) ORG:0x2C
#define SET_STH_WIDTH 0x01 // GPO_STH_WIDTH(0xDE)
#define SET_OEH_START 0xA3 // GPO_OEH_START(0xDF)
#define SET_OEH_WIDTH 0x0B // GPO_OEH_WIDTH(0xE0)
#define SET_OEV_START 0x01 // GPO_OEV_START(0xE1)
#define SET_OEV_WIDTH 0x6D // GPO_OEV_WIDTH(0xE2)
#define SET_CKV_START 0x2D // GPO_CKV_START(0xE3)
#define SET_CKV_START2 0x04 // GPO_CKV_START2(0xE4)
#define SET_CKV_WIDTH 0x5F // GPO_CKV_WIDTH(0xE5)
#define SET_STV_LINE_TH 0x46 // GPO_STV_LINE_TH(0xE6)
#define SET_STV_START 0x29 // GPO_STV_START(0xE7)
#define SET_STV_WIDTH 0x00 // GPO_STV_WIDTH(0xE8)
#define SET_OEV2_START 0x04 // GPO_OEV2_START(0xE9)
#define SET_OEV3_START 0x04 // GPO_OEV3_START(0xEA)
#define SET_H_ST_DLY_L 0x04 // H_ST_DLY_L(0xEB)
#define SET_H_ST_DLY_H 0xA4 // H_ST_DLY_H(0xEC)
#define SET_CLK_DLY_SYNC_OUT 0x00 // CLK_DLY_SYNC_OUT(0xED)
#define SET_CKV_END2 0x28 // GPO_CKV_END2(0xEE)
#define SET_Q1H 0x00 // Q1H_SETTING(0xEF)
#define SET_OEV2_WIDTH 0x54 // GPO_OEV2_WIDTH(0xCD)
#define SET_OEV3_WIDTH 0x54 // GPO_OEV3_WIDTH(0xCE)
#define SET_OEV_DELTA 0x54 // GPO_OEV_DELTA(0xCF)
// VCOM setting
#define SET_BVOM_DC 0xA0 //DEF_VCOM_DC // BVOM_DC(0x43) //Tina11282008
#define SET_BVOM_OUT 0x58 //DEF_VCOM_AC // BVOM_OUT(0x44)
// DAC setting
#define SET_VDAC_ADJ1 0x07 // VADC_ADJ1(0xAA)
#define SET_VDAC_ADJ2 0x00 // VDAC_ADJ2(0xAB)
// Video decoder
#define _656_PLL_VALUE 0xA4 //BK2_9D_DPL_NSPL_HIGH
#define COCTRL1_VALUE 0x20
#define SVD_EN_VALUE0 0x40 //BK2_1A_SVD_EN
#define BK1_7B_TERM_SEL_VALUE 0xE4
#define BK1_7C_CROING_VALUE 0x64
#define PANEL_SYNC_MODE_1 0
#define ENABLE_VSYNC_CTL_AUTO_H_TOTAL 1
#define ENABLE_CHECK_AUTO_H_TOTAL 0
#define ENABLE_OVER_SCAN 1
#define VD_OVER_SCAN_H 10 // 1.0%
#define VD_OVER_SCAN_V 20 // 1.0%
#define BK0_03_SYNC_Sample_Edge 0x98
#define PANEL_LOCK_Y_LINE 2
#ifdef _VDCaptureSetting_
code _CaptureVideoWinType tMsVDCapture[SIG_NUMS] = // For internal VD
{
{0x85, 0x0E, 1340, 480}, // NSTC
{0x85, 0x1A, 1340, 576}, // PAL
{0x85, 0x1A, 1340, 576}, // SECAM
{0x85, 0x1A, 1340, 480}, // NTSC-443
{0x85, 0x1A, 1340, 480}, // PAL-60
{0x85, 0x1A, 1340, 480}, // PAL-M
{0x85, 0x1A, 1340, 576}, // PAL-Nc
};
code _CaptureSvideoWinStartType tSvideoCaptureStart[SIG_NUMS] = // For internal VD
{
{0x73, 0x06}, // NSTC
{0x8b, 0x0c}, // PAL
{0x8b, 0x0c}, // SECAM
{0x73, 0x06}, // NTSC-443
{0x8b, 0x0c}, // PAL-60
{0x8b, 0x0c}, // PAL-M
{0x8b, 0x0c}, // PAL-Nc
};
#endif
#define FreeRunHTotal 0x4FD// 0x3FD//0x280
#define PalHTotal 0x2A9
#define NtscHTotal 0x2B1
#ifdef EnableUseModeTbl
RegUnitType code tENDModeTbl[]=
{
{_END_OF_TBL_,0},
};
RegUnitType code tNtscModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code tPalModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
#if CCIR656_ENABLE
RegUnitType code tCCIR656_PalModeTbl[]=
{//Reg Vale
{BK0_05_SPRVST_L, 0x1e},
{BK0_06_SPRVST_H, 0x00},
{BK0_07_SPRHST_L, 0x45},
{BK0_08_SPRHST_H, 0x01},
{BK0_0B_SPRHDC_L, 0xc4},
{BK0_27_OPL_SET2, 0x36},
{BK0_30_SRH_L, 0x00},
{BK0_31_SRH_M, 0x36},
{BK0_32_SRH_H, 0xcb},
{BK0_34_SRV_M, 0x78},
{_END_OF_TBL_, 0x00},
};
RegUnitType code tCCIR656_NtscModeTbl[]=
{//Reg Vale
{BK0_05_SPRVST_L, 0x1e},
{BK0_06_SPRVST_H, 0x00},
{BK0_07_SPRHST_L, 0x45},
{BK0_08_SPRHST_H, 0x01},
{BK0_0B_SPRHDC_L, 0xb1},
{BK0_30_SRH_L, 0x00},
{BK0_31_SRH_M, 0x20},
{BK0_32_SRH_H, 0xc9},
{_END_OF_TBL_, 0x00},
};
#endif
#if VGA_ENABLE
RegUnitType code t640_480_60Hz_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code t640_480_72Hz_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code t640_480_75Hz_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_56Hz_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_60Hz_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_72Hz_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_75Hz_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1024_768_60Hz_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1024_768_70Hz_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1024_768_75Hz_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
#endif
RegUnitType code tTVSnowModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_33_SRV_L,0x00},
{BK0_34_SRV_M,0x60},
{BK0_35_SRV_H,0x87},
{BK0_40_VFDEST_L,0x10},
{BK0_41_VFDEST_H,0x00},
{BK0_44_VFDEEND_L,0x67},
{BK0_45_VFDEEND_H,0x02},
{BK0_4A_SIVEND_L,0x67},
{BK0_4B_SIVEND_H,0x02},
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