📄 mst705Ȧ
字号:
#include "ms_reg.h"
#ifndef __CM106_V_H
#define __CM106_V_H
#include "devvd.h"
#define PanelName "PNL_CM106_V"
#define WidePanel 1
#define PANEL_DOT_WIDTH 92.5 // unit: um
#define PANEL_DOT_HEIGHT 277.5 // unit: um
#define PanelDither 1
#define PANEL_TTL 0
#define PANEL_DIGITAL_TCON 0
#define PANEL_ANALOG_TCON 0
#define PANEL_LVDS 1
#define PANEL_LVDS_TI_MODE 0
#define PANEL_SWAP_LVDS_POL 0
#define PANEL_SWAP_LVDS_CH 0
#define PanelSwapRB 0xFF
#define PanelSwap8BitML 0
#define PanelSwap6BitML 0//0xFF
#define PanelDClkDelay 0//0
#define PanelInvDE 0
#define PanelInvDClk 0//0
#define PanelInvHSync 0
#define PanelInvVSync 0
// driving current setting 0==>4mA, 1==>6mA, 2==>8mA ,3==>12mA
#define PanelDCLKCurrent 1 // Dclk current
#define PanelDECurrent 1 // DE signal current
#define PANELHSCURRENT 1 // HSYNC current
#define PANELVSCURRENT 1 // VSYNC current
#define PANELBMCURRENT 1 // B data High-Nibble current
#define PANELBLCURRENT 1 // B data Low-Nibble current
#define PANELGMCURRENT 1 // G data High-Nibble current
#define PANELGLCURRENT 1 // G data Low-Nibble current
#define PANELRMCURRENT 1 // R data High-Nibble current
#define PANELRLCURRENT 1 // R data Low-Nibble current
#define PANELADCLKCURRENT 1 // Analog Panel DCLK current
#define PanelOnTiming1 0//100 // time between panel & data while turn on power
#define PanelOnTiming2 50//100 // time between data & back light while turn on power
#define PanelOffTiming1 20 // time between back light & data while turn off power
#define PanelOffTiming2 0//20 // time between data & panel while turn off power
#define PanelHSyncWidth 32//20
#define PanelHSyncBackPorch 212//39
#define PanelVSyncWidth 4//6
#define PanelVSyncBackPorch 35//24
#define PANEL_DE_VSTART 0
#define PanelHStart (PanelHSyncWidth+PanelHSyncBackPorch)
#define PanelVStart (PanelVSyncWidth+PanelVSyncBackPorch)
#define PanelWidth 1024
#define PanelHeight 600
#define PanelHTotal 1200//1056
#define PanelVTotal 625
#define PanelVdeEnd PanelHeight
#define PanelVSiEnd PanelHeight
#define PanelMinHTotal 1300//1600
#define PanelDCLK (((DWORD)PanelHTotal*PanelVTotal*60)/1000000)
///////////////////////////////////////////////////////
// TCON setting
///////////////////////////////////////////////////////
// PTC Mode setting
#define SET_PTC_MODE1 0x8C // PTC_MODE1(0xD0)
#define SET_PTC_MODE2_NOR 0x16 // BK1_D1_PTC_MODE2(0xD1) ORG:0x18
#define SET_PTC_MODE2_INV 0x13 // BK1_D1_PTC_MODE2(0xD1) ORG:0x18
#define SET_PTC_MODE3 0x82 // PTC_MODE3(0xD2)
// PTC Timming Setting
#define SET_FRP_TRAN 0x02 // GPO_FRP_TRAN(0xDC)
#define SET_STH_START 0x6F // GPO_STH_START(0xDD)
#define SET_STH_WIDTH 0x01 // GPO_STH_WIDTH(0xDE)
#define SET_OEH_START 0x6E // GPO_OEH_START(0xDF)
#define SET_OEH_WIDTH 0x07 // GPO_OEH_WIDTH(0xE0)
#define SET_OEV_START 0x6C // GPO_OEV_START(0xE1)
#define SET_OEV_WIDTH 0x29 // GPO_OEV_WIDTH(0xE2)
#define SET_CKV_START 0x6D // GPO_CKV_START(0xE3)
#define SET_CKV_START2 0x00 // GPO_CKV_START2(0xE4)
#define SET_CKV_WIDTH 0x1C // GPO_CKV_WIDTH(0xE5)
#define SET_STV_LINE_TH 0x4E // GPO_STV_LINE_TH(0xE6)
#define SET_STV_START 0x6F // GPO_STV_START(0xE7)
#define SET_STV_WIDTH 0x00 // GPO_STV_WIDTH(0xE8)
#define SET_OEV2_START 0x00 // GPO_OEV2_START(0xE9)
#define SET_OEV3_START 0x00 // GPO_OEV3_START(0xEA)
#define SET_H_ST_DLY_L 0x00 // H_ST_DLY_L(0xEB)
#define SET_H_ST_DLY_H 0x00 // H_ST_DLY_H(0xEC)
#define SET_CLK_DLY_SYNC_OUT 0x00 // CLK_DLY_SYNC_OUT(0xED)
#define SET_CKV_END2 0x00 // GPO_CKV_END2(0xEE)
#define SET_Q1H 0x00 // Q1H_SETTING(0xEF)
#define SET_OEV2_WIDTH 0x54 // GPO_OEV2_WIDTH(0xCD)
#define SET_OEV3_WIDTH 0x54 // GPO_OEV3_WIDTH(0xCE)
#define SET_OEV_DELTA 0x54 // GPO_OEV_DELTA(0xCF)
// VCOM setting
#define SET_BVOM_DC 0xEF //DEF_VCOM_DC // BVOM_DC(0x43)
#define SET_BVOM_OUT 0xFF //DEF_VCOM_AC // BVOM_OUT(0x44)
// DAC setting
#define SET_VDAC_ADJ1 0x00 // VADC_ADJ1(0xAA)
#define SET_VDAC_ADJ2 0x00 // VDAC_ADJ2(0xAB)
// Video decoder
#define _656_PLL_VALUE 0x71 //BK2_9D_DPL_NSPL_HIGH
#define COCTRL1_VALUE 0x20
#define SVD_EN_VALUE0 0x40 //BK2_1A_SVD_EN
#define BK1_7B_TERM_SEL_VALUE 0xB5
#define BK1_7C_CROING_VALUE 0x64
#define PANEL_SYNC_MODE_1 0
#define ENABLE_VSYNC_CTL_AUTO_H_TOTAL 1
#define ENABLE_CHECK_AUTO_H_TOTAL 1
#define ENABLE_OVER_SCAN 1
#define VD_OVER_SCAN_H 00 // 1.0%
#define VD_OVER_SCAN_V 17 // 1.0%
#define BK0_03_SYNC_Sample_Edge 0x98
#ifdef _VDCaptureSetting_
code _CaptureVideoWinType tMsVDCapture[SIG_NUMS] = // For internal VD
{
{0x79, 0x05, (DWORD)PanelWidth, 480}, // NSTC
{0x81, 0x0C, (DWORD)PanelWidth, 576}, // PAL
{0x81, 0x0A, (DWORD)PanelWidth, 576}, // SECAM
{0x79, 0x05, (DWORD)PanelWidth, 480}, // NTSC-443
{0x79, 0x05, (DWORD)PanelWidth, 480}, // PAL-60
{0x79, 0x05, (DWORD)PanelWidth, 480}, // PAL-M
{0x81, 0x0C, (DWORD)PanelWidth, 576}, // PAL-Nc
};
code _CaptureSvideoWinStartType tSvideoCaptureStart[SIG_NUMS] = // For internal VD
{
{0x73, 0x06}, // NSTC
{0x8b, 0x0c}, // PAL
{0x8b, 0x0c}, // SECAM
{0x73, 0x06}, // NTSC-443
{0x8b, 0x0c}, // PAL-60
{0x8b, 0x0c}, // PAL-M
{0x8b, 0x0c}, // PAL-Nc
};
#endif
#define FreeRunHTotal 0x437
#define PalHTotal 0x4A7
#define NtscHTotal 0x593
#ifdef EnableUseModeTbl
RegUnitType code tENDModeTbl[]=
{
{_END_OF_TBL_,0},
};
RegUnitType code tNtscModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_40_VFDEST_L, LOBYTE(PANEL_DE_VSTART)}, // vertical DE start
{BK0_41_VFDEST_H, HIBYTE(PANEL_DE_VSTART)}, // vertical DE start
{BK0_50_VSST_L, 0xFF}, // vsync start position
{BK0_51_VSST_H, 0x01},
{BK0_52_VSEND_L, 0x05}, // vsync start position
{BK0_53_VSEND_H, 0x02},
{_END_OF_TBL_, 0x00},
};
RegUnitType code tPalModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_40_VFDEST_L, LOBYTE(PANEL_DE_VSTART)}, // vertical DE start
{BK0_41_VFDEST_H, HIBYTE(PANEL_DE_VSTART)}, // vertical DE start
{BK0_50_VSST_L, 0xF8}, // vsync start position
{BK0_51_VSST_H, 0x01},
{BK0_52_VSEND_L, 0x00}, // vsync start position
{BK0_53_VSEND_H, 0x02},
{_END_OF_TBL_, 0x00},
};
#if VGA_ENABLE
RegUnitType code t640_480_60Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x08},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t640_480_72Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x08},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t640_480_75Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x08},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_56Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0B},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_60Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0B},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_72Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0B},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_75Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0B},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1024_768_60Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0E},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1024_768_70Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0E},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1024_768_75Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0E},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
#endif
#if 0//YPBPR_ENABLE
RegUnitType code t576i_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x05},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t576p_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0a},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t480i_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x04},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t480p_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x08},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t720p_50Hz_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0c},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t720p_60Hz_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0b},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -