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📄 sfr_r81b.h

📁 本代码以低成本的瑞萨单片机为主控制器
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#define    p3_3          p3_addr.bit.b3        /* Port P33 bit */
#define    p3_4          p3_addr.bit.b4        /* Port P34 bit */
#define    p3_5          p3_addr.bit.b5        /* Port P35 bit */
#define    p3_7          p3_addr.bit.b7        /* Port P37 bit */

/*------------------------------------------------------
  Port P3 direction register
------------------------------------------------------*/
union byte_def pd3_addr;
#define    pd3           pd3_addr.byte

#define    pd3_3         pd3_addr.bit.b3       /* Port P33 direction bit */
#define    pd3_4         pd3_addr.bit.b4       /* Port P34 direction bit */
#define    pd3_5         pd3_addr.bit.b5       /* Port P35 direction bit */
#define    pd3_7         pd3_addr.bit.b7       /* Port P37 direction bit */

/*------------------------------------------------------
  Port P4 register
------------------------------------------------------*/
union byte_def p4_addr;
#define    p4            p4_addr.byte

#define    p4_2          p4_addr.bit.b2        /* Port P42 bit */
#define    p4_5          p4_addr.bit.b5        /* Port P45 bit */
#define    p4_6          p4_addr.bit.b6        /* Port P46 bit */
#define    p4_7          p4_addr.bit.b7        /* Port P47 bit */

/*------------------------------------------------------
  Port P4 direction register
------------------------------------------------------*/
union byte_def pd4_addr;
#define    pd4           pd4_addr.byte

#define    pd4_5         pd4_addr.bit.b5       /* Port P45 direction bit */

/*------------------------------------------------------
  Port mode register
------------------------------------------------------*/
union byte_def pmr_addr;
#define    pmr           pmr_addr.byte

#define    ssisel        pmr_addr.bit.b3       /* SSI Signal Pin Select bit */
#define    iicsel        pmr_addr.bit.b7       /* SSU / I2C bus Switch bit */

/*------------------------------------------------------
  Pull-up control register0
------------------------------------------------------*/
union byte_def pur0_addr;
#define    pur0          pur0_addr.byte

#define    pu02          pur0_addr.bit.b2      /* P10 to P13 pull-up */
#define    pu03          pur0_addr.bit.b3      /* P14 to P17 pull-up */
#define    pu06          pur0_addr.bit.b6      /* P33 pull-up */
#define    pu07          pur0_addr.bit.b7      /* P34, P35, P37 pull-up */

/*------------------------------------------------------
  Pull-up control register1
------------------------------------------------------*/
union byte_def pur1_addr;
#define    pur1          pur1_addr.byte

#define    pu11          pur1_addr.bit.b1      /* P45 pull-up */

/*------------------------------------------------------
  Port P1 drive capacity control register
------------------------------------------------------*/
union byte_def drr_addr;
#define    drr           drr_addr.byte

#define    drr0          drr_addr.bit.b0       /* P10 capacity */
#define    drr1          drr_addr.bit.b1       /* P11 capacity */
#define    drr2          drr_addr.bit.b2       /* P12 capacity */
#define    drr3          drr_addr.bit.b3       /* P13 capacity */

/*------------------------------------------------------
  Timer C output control register
------------------------------------------------------*/
union byte_def tcout_addr;
#define    tcout         tcout_addr.byte

#define    tcout0        tcout_addr.bit.b0     /* CMP output enable bit0 */
#define    tcout1        tcout_addr.bit.b1     /* CMP output enable bit1 */
#define    tcout2        tcout_addr.bit.b2     /* CMP output enable bit2 */
#define    tcout3        tcout_addr.bit.b3     /* CMP output enable bit3 */
#define    tcout4        tcout_addr.bit.b4     /* CMP output enable bit4 */
#define    tcout5        tcout_addr.bit.b5     /* CMP output enable bit5 */
#define    tcout6        tcout_addr.bit.b6     /* CMP output reverse bit0 */
#define    tcout7        tcout_addr.bit.b7     /* CMP output reverse bit1 */

/*------------------------------------------------------
  Flash mamory control register4
------------------------------------------------------*/
union byte_def fmr4_addr;
#define    fmr4          fmr4_addr.byte

#define    fmr40         fmr4_addr.bit.b0      /* Erase-suspend function enable bit */
#define    fmr41         fmr4_addr.bit.b1      /* Erase-suspend request bit */
#define    fmr42         fmr4_addr.bit.b2      /* Program-suspend request bit */
#define    fmr43         fmr4_addr.bit.b3      /* Erase command flag */
#define    fmr44         fmr4_addr.bit.b4      /* Program command flag */
#define    fmr46         fmr4_addr.bit.b6      /* Read status flag */
#define    fmr47         fmr4_addr.bit.b7      /* Low-Power consumption read mode enable bit */

/*------------------------------------------------------
  Flash mamory control register1
------------------------------------------------------*/
union byte_def fmr1_addr;
#define    fmr1          fmr1_addr.byte

#define    fmr11         fmr1_addr.bit.b1      /* EW1 mode select bit */
#define    fmr15         fmr1_addr.bit.b5      /* Block0 rewrite disable bit */
#define    fmr16         fmr1_addr.bit.b6      /* Block1 rewrite disable bit */

/*------------------------------------------------------
  Flash mamory control register0
------------------------------------------------------*/
union byte_def fmr0_addr;
#define    fmr0          fmr0_addr.byte

#define    fmr00         fmr0_addr.bit.b0      /* RY/BY status flag */
#define    fmr01         fmr0_addr.bit.b1      /* CPU rewrite mode select bit */
#define    fmr02         fmr0_addr.bit.b2      /* Block0 and 1 rewrite enable bit */
#define    fmstp         fmr0_addr.bit.b3      /* Flash memory stop bit */
#define    fmr06         fmr0_addr.bit.b6      /* Program status flag  */
#define    fmr07         fmr0_addr.bit.b7      /* Erase status flag */

/*------------------------------------------------------
  Interrupt control register
------------------------------------------------------*/
union{
  struct{
    char  ilvl0:1;                             /* Interrupt priority level select bit */
    char  ilvl1:1;                             /* Interrupt priority level select bit */
    char  ilvl2:1;                             /* Interrupt priority level select bit */
    char  ir:1;                                /* Interrupt request bit */
    char  pol:1;                               /* Polarity select bit */
    char  b5:1;
    char  b6:1;
    char  b7:1;
  }bit;
  char  byte;
} kupic_addr, adic_addr, cmp1ic_addr, s0tic_addr, s0ric_addr, s1tic_addr, s1ric_addr, txic_addr,
  tzic_addr, int1ic_addr, int3ic_addr, tcic_addr, cmp0ic_addr, int0ic_addr;

/*------------------------------------------------------
  Key input interrupt control register
------------------------------------------------------*/
#define     kupic         kupic_addr.byte

#define     ilvl0_kupic   kupic_addr.bit.ilvl0
#define     ilvl1_kupic   kupic_addr.bit.ilvl1
#define     ilvl2_kupic   kupic_addr.bit.ilvl2
#define     ir_kupic      kupic_addr.bit.ir

/*------------------------------------------------------
  Comparator conversion interrupt control register
------------------------------------------------------*/
#define     adic          adic_addr.byte

#define     ilvl0_adic    adic_addr.bit.ilvl0
#define     ilvl1_adic    adic_addr.bit.ilvl1
#define     ilvl2_adic    adic_addr.bit.ilvl2
#define     ir_adic       adic_addr.bit.ir

/*------------------------------------------------------
  Compare 1 interrupt control register
------------------------------------------------------*/
#define     cmp1ic        cmp1ic_addr.byte

#define     ilvl0_cmp1ic  cmp1ic_addr.bit.ilvl0
#define     ilvl1_cmp1ic  cmp1ic_addr.bit.ilvl1
#define     ilvl2_cmp1ic  cmp1ic_addr.bit.ilvl2
#define     ir_cmp1ic     cmp1ic_addr.bit.ir

/*------------------------------------------------------
  UART0 transmit interrupt control register
------------------------------------------------------*/
#define     s0tic         s0tic_addr.byte

#define     ilvl0_s0tic   s0tic_addr.bit.ilvl0
#define     ilvl1_s0tic   s0tic_addr.bit.ilvl1
#define     ilvl2_s0tic   s0tic_addr.bit.ilvl2
#define     ir_s0tic      s0tic_addr.bit.ir

/*------------------------------------------------------
  UART0 receive interrupt control register
------------------------------------------------------*/
#define     s0ric         s0ric_addr.byte

#define     ilvl0_s0ric   s0ric_addr.bit.ilvl0
#define     ilvl1_s0ric   s0ric_addr.bit.ilvl1
#define     ilvl2_s0ric   s0ric_addr.bit.ilvl2
#define     ir_s0ric      s0ric_addr.bit.ir

/*------------------------------------------------------
  UART1 transmit interrupt control register
------------------------------------------------------*/
#define     s1tic         s1tic_addr.byte

#define     ilvl0_s1tic   s1tic_addr.bit.ilvl0
#define     ilvl1_s1tic   s1tic_addr.bit.ilvl1
#define     ilvl2_s1tic   s1tic_addr.bit.ilvl2
#define     ir_s1tic      s1tic_addr.bit.ir

/*------------------------------------------------------
  UART1 receive interrupt control register
------------------------------------------------------*/
#define     s1ric         s1ric_addr.byte

#define     ilvl0_s1ric   s1ric_addr.bit.ilvl0
#define     ilvl1_s1ric   s1ric_addr.bit.ilvl1
#define     ilvl2_s1ric   s1ric_addr.bit.ilvl2
#define     ir_s1ric      s1ric_addr.bit.ir

/*------------------------------------------------------
  Timer X interrupt control register
------------------------------------------------------*/
#define     txic          txic_addr.byte

#define     ilvl0_txic    txic_addr.bit.ilvl0
#define     ilvl1_txic    txic_addr.bit.ilvl1
#define     ilvl2_txic    txic_addr.bit.ilvl2
#define     ir_txic       txic_addr.bit.ir

/*------------------------------------------------------
  Timer Z interrupt control register
------------------------------------------------------*/
#define     tzic          tzic_addr.byte

#define     ilvl0_tzic    tzic_addr.bit.ilvl0
#define     ilvl1_tzic    tzic_addr.bit.ilvl1
#define     ilvl2_tzic    tzic_addr.bit.ilvl2
#define     ir_tzic       tzic_addr.bit.ir

/*------------------------------------------------------
  INT1 interrupt control register
------------------------------------------------------*/
#define     int1ic        int1ic_addr.byte

#define     ilvl0_int1ic  int1ic_addr.bit.ilvl0
#define     ilvl1_int1ic  int1ic_addr.bit.ilvl1
#define     ilvl2_int1ic  int1ic_addr.bit.ilvl2
#define     ir_int1ic     int1ic_addr.bit.ir
/*------------------------------------------------------
  INT3 interrupt control register
------------------------------------------------------*/
#define     int3ic        int3ic_addr.byte

#define     ilvl0_int3ic  int3ic_addr.bit.ilvl0
#define     ilvl1_int3ic  int3ic_addr.bit.ilvl1
#define     ilvl2_int3ic  int3ic_addr.bit.ilvl2
#define     ir_int3ic     int3ic_addr.bit.ir
/*------------------------------------------------------
  Timer C interrupt control register
------------------------------------------------------*/
#define     tcic          tcic_addr.byte

#define     ilvl0_tcic    tcic_addr.bit.ilvl0
#define     ilvl1_tcic    tcic_addr.bit.ilvl1
#define     ilvl2_tcic    tcic_addr.bit.ilvl2
#define     ir_tcic       tcic_addr.bit.ir

/*------------------------------------------------------
  Compare 0 interrupt control register
------------------------------------------------------*/
#define     cmp0ic        cmp0ic_addr.byte

#define     ilvl0_cmp0ic  cmp0ic_addr.bit.ilvl0
#define     ilvl1_cmp0ic  cmp0ic_addr.bit.ilvl1
#define     ilvl2_cmp0ic  cmp0ic_addr.bit.ilvl2
#define     ir_cmp0ic     cmp0ic_addr.bit.ir

/*------------------------------------------------------
  INT0 interrupt control register
------------------------------------------------------*/
#define     int0ic        int0ic_addr.byte

#define     ilvl0_int0ic  int0ic_addr.bit.ilvl0

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