📄 sfr_r81b.h
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union byte_def u0brg_addr;
#define u0brg u0brg_addr.byte
/*------------------------------------------------------
UART1 bit rate generator
------------------------------------------------------*/
union byte_def u1brg_addr;
#define u1brg u1brg_addr.byte
/*------------------------------------------------------
UART transmit/receive control register2
------------------------------------------------------*/
union byte_def ucon_addr;
#define ucon ucon_addr.byte
#define u0irs ucon_addr.bit.b0 /* UART0 transmit interrupt cause select bit */
#define u1irs ucon_addr.bit.b1 /* UART1 transmit interrupt cause select bit */
#define u0rrm ucon_addr.bit.b2 /* UART0 continuous receive mode enable bit */
#define u1sel0 ucon_addr.bit.b4 /* UART1 pin (P3_7/TXD1,P4_5/RXD1) select bit */
#define u1sel1 ucon_addr.bit.b5 /* UART1 pin (P3_7/TXD1,P4_5/RXD1) select bit */
#define cntrsel ucon_addr.bit.b7 /* Cntr0 signal pin select bit */
/*------------------------------------------------------
SS control register H
------------------------------------------------------*/
union byte_def sscrh_addr;
#define sscrh sscrh_addr.byte
#define cks0_sscrh sscrh_addr.bit.b0 /* Transfer clock rate select bit */
#define cks1_sscrh sscrh_addr.bit.b1 /* Transfer clock rate select bit */
#define cks2_sscrh sscrh_addr.bit.b2 /* Transfer clock rate select bit */
#define mss_sscrh sscrh_addr.bit.b5 /* Master/Slave device select bit */
#define rsstp_sscrh sscrh_addr.bit.b6 /* Receive single stop bit */
/*------------------------------------------------------
SS control register L
------------------------------------------------------*/
union byte_def sscrl_addr;
#define sscrl sscrl_addr.byte
#define sres_sscrl sscrl_addr.bit.b1 /* SSUA control part reset bit */
#define solp_sscrl sscrl_addr.bit.b4 /* SOL write protect bit */
#define sol_sscrl sscrl_addr.bit.b5 /* Serial data output value setting bit */
/*------------------------------------------------------
SS mode register
------------------------------------------------------*/
union byte_def ssmr_addr;
#define ssmr ssmr_addr.byte
#define bc0_ssmr ssmr_addr.bit.b0 /* Bit counter 2 to 0*/
#define bc1_ssmr ssmr_addr.bit.b1 /* Bit counter 2 to 0*/
#define bc2_ssmr ssmr_addr.bit.b2 /* Bit counter 2 to 0*/
#define cphs_ssmr ssmr_addr.bit.b5 /* SSCK clock phase select bit */
#define cpos_ssmr ssmr_addr.bit.b6 /* SSCK clock polarity select bit */
#define mls_ssmr ssmr_addr.bit.b7 /* MSB first/ LSB first select bit */
/*------------------------------------------------------
SS enable register
------------------------------------------------------*/
union byte_def sser_addr;
#define sser sser_addr.byte
#define ceie_sser sser_addr.bit.b0 /* Conflict error interrupt enable bit */
#define re_sser sser_addr.bit.b3 /* Receive enable bit */
#define te_sser sser_addr.bit.b4 /* Transmit enable bit */
#define rie_sser sser_addr.bit.b5 /* Receive interrupt enable bit */
#define teie_sser sser_addr.bit.b6 /* Transmit end interrupt enable bit */
#define tie_sser sser_addr.bit.b7 /* Transmit interrupt enable bit */
/*------------------------------------------------------
SS status register
------------------------------------------------------*/
union byte_def sssr_addr;
#define sssr sssr_addr.byte
#define ce_sssr sssr_addr.bit.b0 /* Conflict error flag */
#define orer_sssr sssr_addr.bit.b2 /* Overrun error flag */
#define rdrf_sssr sssr_addr.bit.b5 /* Receive data register ful */
#define tend_sssr sssr_addr.bit.b6 /* Transmit end */
#define tdre_sssr sssr_addr.bit.b7 /* Transmit data empty */
/*------------------------------------------------------
SS mode register 2
------------------------------------------------------*/
union byte_def ssmr2_addr;
#define ssmr2 ssmr2_addr.byte
#define ssums_ssmr2 ssmr2_addr.bit.b0 /* SSUA mode select bit */
#define csos_ssmr2 ssmr2_addr.bit.b1 /* SCS pin open drain output select bit */
#define soos_ssmr2 ssmr2_addr.bit.b2 /* SSO pin open drain output select bit */
#define sckos_ssmr2 ssmr2_addr.bit.b3 /* SSCK pin open drain output select bit */
#define css0_ssmr2 ssmr2_addr.bit.b4 /* SCS pin selsct bit */
#define css1_ssmr2 ssmr2_addr.bit.b5 /* SCS pin select bit */
#define scks_ssmr2 ssmr2_addr.bit.b6 /* SSCK pin select bit */
#define bide_ssmr2 ssmr2_addr.bit.b7 /* Bidirectional mode enable bit */
/*------------------------------------------------------
SS transmit data register
------------------------------------------------------*/
union byte_def sstdr_addr;
#define sstdr sstdr_addr.byte
/*------------------------------------------------------
SS receive data register
------------------------------------------------------*/
union byte_def ssrdr_addr;
#define ssrdr ssrdr_addr.byte
/*------------------------------------------------------
IIC bus control register 1
------------------------------------------------------*/
union byte_def iccr1_addr;
#define iccr1 iccr1_addr.byte
#define cks0_iccr1 iccr1_addr.bit.b0 /* Transmit clock select bit 3 to 0 */
#define cks1_iccr1 iccr1_addr.bit.b1 /* Transmit clock select bit 3 to 0 */
#define cks2_iccr1 iccr1_addr.bit.b2 /* Transmit clock select bit 3 to 0 */
#define cks3_iccr1 iccr1_addr.bit.b3 /* Transmit clock select bit 3 to 0 */
#define trs_iccr1 iccr1_addr.bit.b4 /* Transfer/receive select bit */
#define mst_iccr1 iccr1_addr.bit.b5 /* Master/slave select bit */
#define rcvd_iccr1 iccr1_addr.bit.b6 /* Receive disable bit */
#define ice_iccr1 iccr1_addr.bit.b7 /* IIC bus interface 2A enable bit */
/*------------------------------------------------------
IIC bus control register 2
------------------------------------------------------*/
union byte_def iccr2_addr;
#define iccr2 iccr2_addr.byte
#define iicrst_iccr2 iccr2_addr.bit.b1 /* IIC control part reset bit */
#define sclo_iccr2 iccr2_addr.bit.b3 /* SCL monitor flag */
#define sdaop_iccr2 iccr2_addr.bit.b4 /* SDAO write protect bit */
#define sdao_iccr2 iccr2_addr.bit.b5 /* SDA output value control bit */
#define scp_iccr2 iccr2_addr.bit.b6 /* Start/Stop condition generation disable bit */
#define bbsy_iccr2 iccr2_addr.bit.b7 /* Bus busy bit */
/*------------------------------------------------------
IIC bus mode register
------------------------------------------------------*/
union byte_def icmr_addr;
#define icmr icmr_addr.byte
#define bc0_icmr icmr_addr.bit.b0 /* Bit counter 2 to 0 */
#define bc1_icmr icmr_addr.bit.b1 /* Bit Counter 2 to 0 */
#define bc2_icmr icmr_addr.bit.b2 /* Bit Counter 2 to 0 */
#define bcwp_icmr icmr_addr.bit.b3 /* BC write protect bit */
#define wait_icmr icmr_addr.bit.b6 /* Wait insertion bit */
#define mls_icmr icmr_addr.bit.b7 /* MSB-First/LSB-First select */
/*------------------------------------------------------
IIC bus interrupt enable register
------------------------------------------------------*/
union byte_def icier_addr;
#define icier icier_addr.byte
#define ackbt_icier icier_addr.bit.b0 /* Transmit acknow ledge select bit */
#define ackbr_icier icier_addr.bit.b1 /* Receive acknow ledge bit */
#define acke_icier icier_addr.bit.b2 /* Acknow ledge bit Judgement Select Bit */
#define stie_icier icier_addr.bit.b3 /* Stop condition detection interrupt enable bit */
#define nakie_icier icier_addr.bit.b4 /* NACK receive interrupt enable bit */
#define rie_icier icier_addr.bit.b5 /* Receive interrupt enable bit */
#define teie_icier icier_addr.bit.b6 /* Transmit end interrupt enable bit */
#define tie_icier icier_addr.bit.b7 /* Transmit interrupt enable bit */
/*------------------------------------------------------
IIC bus status register
------------------------------------------------------*/
union byte_def icsr_addr;
#define icsr icsr_addr.byte
#define adz_icsr icsr_addr.bit.b0 /* General call address recognition flag */
#define aas_icsr icsr_addr.bit.b1 /* Slave address recognition flag */
#define al_icsr icsr_addr.bit.b2 /* Arbitration lost flag */
#define stop_icsr icsr_addr.bit.b3 /* Stop condition detection flag */
#define nackf_icsr icsr_addr.bit.b4 /* No acknow ledge detection flag */
#define rdrf_icsr icsr_addr.bit.b5 /* Receive data register full */
#define tend_icsr icsr_addr.bit.b6 /* Transmit end */
#define tdre_icsr icsr_addr.bit.b7 /* Transmit data empty */
/*------------------------------------------------------
Slave address register
------------------------------------------------------*/
union byte_def sar_addr;
#define sar sar_addr.byte
#define fs_sar sar_addr.bit.b0 /* Format select bit */
#define sva0_sar sar_addr.bit.b1 /* Slave address 6 to 0 */
#define sva1_sar sar_addr.bit.b2 /* Slave address 6 to 0 */
#define sva2_sar sar_addr.bit.b3 /* Slave address 6 to 0 */
#define sva3_sar sar_addr.bit.b4 /* Slave address 6 to 0 */
#define sva4_sar sar_addr.bit.b5 /* Slave address 6 to 0 */
#define sva5_sar sar_addr.bit.b6 /* Slave address 6 to 0 */
#define sva6_sar sar_addr.bit.b7 /* Slave address 6 to 0 */
/*------------------------------------------------------
IIC bus transmit data register
------------------------------------------------------*/
union byte_def icdrt_addr;
#define icdrt icdrt_addr.byte
/*------------------------------------------------------
IIC bus receive data register
------------------------------------------------------*/
union byte_def icdrr_addr;
#define icdrr icdrr_addr.byte
/*------------------------------------------------------
A-D control register2
------------------------------------------------------*/
union byte_def adcon2_addr;
#define adcon2 adcon2_addr.byte
#define smp adcon2_addr.bit.b0 /* A-D conversion method select bit */
/*------------------------------------------------------
A-D control register0
------------------------------------------------------*/
union byte_def adcon0_addr;
#define adcon0 adcon0_addr.byte
#define ch0 adcon0_addr.bit.b0 /* Analog input pin select bit */
#define ch1 adcon0_addr.bit.b1 /* Analog input pin select bit */
#define ch2 adcon0_addr.bit.b2 /* Analog input pin select bit */
#define md adcon0_addr.bit.b3 /* A-D operation mode select bit */
#define adgsel0 adcon0_addr.bit.b4 /* A-D input group select bit */
#define adcap adcon0_addr.bit.b5 /* A-D conversion automatic start bit */
#define adst adcon0_addr.bit.b6 /* A-D conversion start flag */
#define cks0 adcon0_addr.bit.b7 /* Frequency select bit0 */
#define cks0_adcon0 cks0
/*------------------------------------------------------
A-D control register1
------------------------------------------------------*/
union byte_def adcon1_addr;
#define adcon1 adcon1_addr.byte
#define bits adcon1_addr.bit.b3 /* 8/10-bit mode select bit */
#define cks1 adcon1_addr.bit.b4 /* Frequency select bit1 */
#define cks1_adcon1 cks1
#define vcut adcon1_addr.bit.b5 /* Vref connect bit */
/*------------------------------------------------------
Port P1 register
------------------------------------------------------*/
union byte_def p1_addr;
#define p1 p1_addr.byte
#define p1_0 p1_addr.bit.b0 /* Port P10 bit */
#define p1_1 p1_addr.bit.b1 /* Port P11 bit */
#define p1_2 p1_addr.bit.b2 /* Port P12 bit */
#define p1_3 p1_addr.bit.b3 /* Port P13 bit */
#define p1_4 p1_addr.bit.b4 /* Port P14 bit */
#define p1_5 p1_addr.bit.b5 /* Port P15 bit */
#define p1_6 p1_addr.bit.b6 /* Port P16 bit */
#define p1_7 p1_addr.bit.b7 /* Port P17 bit */
/*------------------------------------------------------
Port P1 direction register
------------------------------------------------------*/
union byte_def pd1_addr;
#define pd1 pd1_addr.byte
#define pd1_0 pd1_addr.bit.b0 /* Port P10 direction bit */
#define pd1_1 pd1_addr.bit.b1 /* Port P11 direction bit */
#define pd1_2 pd1_addr.bit.b2 /* Port P12 direction bit */
#define pd1_3 pd1_addr.bit.b3 /* Port P13 direction bit */
#define pd1_4 pd1_addr.bit.b4 /* Port P14 direction bit */
#define pd1_5 pd1_addr.bit.b5 /* Port P15 direction bit */
#define pd1_6 pd1_addr.bit.b6 /* Port P16 direction bit */
#define pd1_7 pd1_addr.bit.b7 /* Port P17 direction bit */
/*------------------------------------------------------
Port P3 register
------------------------------------------------------*/
union byte_def p3_addr;
#define p3 p3_addr.byte
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