📄 sfr_r81b.h
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union byte_def aier_addr;
#define aier aier_addr.byte
#define aier0 aier_addr.bit.b0 /* Address match interrupt 0 enable bit */
#define aier1 aier_addr.bit.b1 /* Address match interrupt 1 enable bit */
/*------------------------------------------------------
Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define prcr prcr_addr.byte
#define prc0 prcr_addr.bit.b0 /* Protect bit0 */
#define prc1 prcr_addr.bit.b1 /* Protect bit1 */
#define prc3 prcr_addr.bit.b3 /* Protect bit3 */
/*------------------------------------------------------
Oscillation stop detection register
------------------------------------------------------*/
union byte_def ocd_addr;
#define ocd ocd_addr.byte
#define ocd0 ocd_addr.bit.b0 /* Oscillation stop detection enabble bit */
#define ocd1 ocd_addr.bit.b1 /* Oscillation stop detection enabble bit */
#define ocd2 ocd_addr.bit.b2 /* System clock select bit */
#define ocd3 ocd_addr.bit.b3 /* Clock monitor bit */
/*------------------------------------------------------
Watchdog timer reset register
------------------------------------------------------*/
union byte_def wdtr_addr;
#define wdtr wdtr_addr.byte
/*------------------------------------------------------
Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define wdts wdts_addr.byte
/*------------------------------------------------------
Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define wdc wdc_addr.byte
#define wdc7 wdc_addr.bit.b7 /* Prescaler select bit */
/*------------------------------------------------------
Count source protect mode register
------------------------------------------------------*/
union byte_def cspr_addr;
#define cspr cspr_addr.byte
#define cspro cspr_addr.bit.b7 /* WDT count source protect mode select bit */
/*------------------------------------------------------
INT0 input filter select register
------------------------------------------------------*/
union byte_def int0f_addr;
#define int0f int0f_addr.byte
#define int0f0 int0f_addr.bit.b0 /* INT0 input filter select bit */
#define int0f1 int0f_addr.bit.b1 /* INT0 input filter select bit */
/*------------------------------------------------------
High-speed on-chip oscillator A control register 0
------------------------------------------------------*/
union byte_def hra0_addr;
#define hra0 hra0_addr.byte
#define hra00 hra0_addr.bit.b0 /* High-speed on-chip oscillator A enable bit */
#define hra01 hra0_addr.bit.b1 /* High-speed on-chip oscillator A select bit */
/*------------------------------------------------------
High-speed on-chip oscillator A control register 1
------------------------------------------------------*/
union byte_def hra1_addr;
#define hra1 hra1_addr.byte
/*------------------------------------------------------
High-speed on-chip oscillator A control register 2
------------------------------------------------------*/
union byte_def hra2_addr;
#define hra2 hra2_addr.byte
#define hra20 hra2_addr.bit.b0 /* High-speed on-chip oscillator mode select bit */
#define hra21 hra2_addr.bit.b1 /* High-speed on-chip oscillator mode select bit */
/*------------------------------------------------------
Voltage detection A register 1
------------------------------------------------------*/
union byte_def vca1_addr;
#define vca1 vca1_addr.byte
#define vca13 vca1_addr.bit.b3 /* Voltage detection 2 signal monitor flag */
/*------------------------------------------------------
Voltage detection A register 2
------------------------------------------------------*/
union byte_def vca2_addr;
#define vca2 vca2_addr.byte
#define vca26 vca2_addr.bit.b6 /* Voltage detection 1 enable bit */
#define vca27 vca2_addr.bit.b7 /* Voltage detection 2 enable bit */
/*------------------------------------------------------
Voltage monitor 1 circuit control register
------------------------------------------------------*/
union byte_def vw1c_addr;
#define vw1c vw1c_addr.byte
#define vw1c0 vw1c_addr.bit.b0 /* Voltage monitor 1 reset enable bit */
#define vw1c1 vw1c_addr.bit.b1 /* Voltage Monitor 1 digital filter disable mode select bit */
#define vw1c2 vw1c_addr.bit.b2 /* Voltage change detection flag */
#define vw1c3 vw1c_addr.bit.b3 /* Voltage detection 1 signal monitor flag */
#define vw1f0 vw1c_addr.bit.b4 /* Sampling clock select bit */
#define vw1f1 vw1c_addr.bit.b5 /* Sampling clock select bit */
#define vw1c6 vw1c_addr.bit.b6 /* Voltage monitor 1 circuit mode select bit */
#define vw1c7 vw1c_addr.bit.b7 /* Voltage monitor 1 reset generating condition select bit */
/*------------------------------------------------------
Voltage monitor 2 circuit control register
------------------------------------------------------*/
union byte_def vw2c_addr;
#define vw2c vw2c_addr.byte
#define vw2c0 vw2c_addr.bit.b0 /* Voltage monitor 2 interrupt / reset enable bit */
#define vw2c1 vw2c_addr.bit.b1 /* Voltage monitor 2 digital filter disabled mode select bit */
#define vw2c2 vw2c_addr.bit.b2 /* Voltage change detection flag */
#define vw2c3 vw2c_addr.bit.b3 /* WDT Detection Flag */
#define vw2f0 vw2c_addr.bit.b4 /* Sampling clock select bit */
#define vw2f1 vw2c_addr.bit.b5 /* Sampling clock select bit */
#define vw2c6 vw2c_addr.bit.b6 /* Voltage monitor 2 circuit mode select bit */
#define vw2c7 vw2c_addr.bit.b7 /* Voltage monitor 2 interrupt / reset generating condition select bit */
/*------------------------------------------------------
Timer Z Mode register
------------------------------------------------------*/
union byte_def tzmr_addr;
#define tzmr tzmr_addr.byte
#define tyzmr tyzmr_addr.byte
#define tzmod0 tzmr_addr.bit.b4 /* TimerZ Operation mode bit */
#define tzmod1 tzmr_addr.bit.b5 /* TimerZ Operation mode bit */
#define tzwc tzmr_addr.bit.b6 /* TimerZ write control bit */
#define tzs tzmr_addr.bit.b7 /* TimerZ count start flag */
/*------------------------------------------------------
Timer Z waveform output control register
------------------------------------------------------*/
union byte_def pum_addr;
#define pum pum_addr.byte
#define tzopl pum_addr.bit.b5 /* TimerZ output level latch */
#define inostg pum_addr.bit.b6 /* INT0 pin one-shot trigger control bit */
#define inoseg pum_addr.bit.b7 /* INT0 pin one-shot trigger polarity select bit */
/*------------------------------------------------------
Prescaler Z register
------------------------------------------------------*/
union byte_def prez_addr;
#define prez prez_addr.byte
/*------------------------------------------------------
Timer Z secondary register
------------------------------------------------------*/
union byte_def tzsc_addr;
#define tzsc tzsc_addr.byte
/*------------------------------------------------------
Timer Z primary register
------------------------------------------------------*/
union byte_def tzpr_addr;
#define tzpr tzpr_addr.byte
/*------------------------------------------------------
Timer Z output control register
------------------------------------------------------*/
union byte_def tzoc_addr;
#define tzoc tzoc_addr.byte
#define tyzoc tzoc_addr.byte
#define tzos tzoc_addr.bit.b0 /* TimerZ one-shot start bit */
#define tzocnt tzoc_addr.bit.b2 /* TimerZ programable waveform generation output switching bit */
/*------------------------------------------------------
Timer X mode register
------------------------------------------------------*/
union byte_def txmr_addr;
#define txmr txmr_addr.byte
#define txmod0 txmr_addr.bit.b0 /* Operation mode select bit0 */
#define txmod1 txmr_addr.bit.b1 /* Operation mode select bit1 */
#define r0edg txmr_addr.bit.b2 /* INT1/CNTR0 polarity switching bit */
#define txs txmr_addr.bit.b3 /* TimerX count start flag */
#define txocnt txmr_addr.bit.b4 /* P30/CNTR0 select bit */
#define txmod2 txmr_addr.bit.b5 /* Operation mode select bit2 */
#define txedg txmr_addr.bit.b6 /* Active edge reception flag */
#define txund txmr_addr.bit.b7 /* TimerX under flow flag */
/*------------------------------------------------------
Prescaler X Register
------------------------------------------------------*/
union byte_def prex_addr;
#define prex prex_addr.byte
/*------------------------------------------------------
Timer X Register
------------------------------------------------------*/
union byte_def tx_addr;
#define tx tx_addr.byte
/*------------------------------------------------------
Timer count source setting register
------------------------------------------------------*/
union byte_def tcss_addr;
#define tcss tcss_addr.byte
#define txck0 tcss_addr.bit.b0 /* TimerX count source select bit */
#define txck1 tcss_addr.bit.b1 /* TimerX count source select bit */
#define tzck0 tcss_addr.bit.b4 /* TimerZ count source select bit */
#define tzck1 tcss_addr.bit.b5 /* TimerZ count source select bit */
/*------------------------------------------------------
External interrupt enable register
------------------------------------------------------*/
union byte_def inten_addr;
#define inten inten_addr.byte
#define int0en inten_addr.bit.b0 /* INT0 input enable bit */
#define int0pl inten_addr.bit.b1 /* INT0 input polarity select bit */
/*------------------------------------------------------
Key input enable register
------------------------------------------------------*/
union byte_def kien_addr;
#define kien kien_addr.byte
#define ki0en kien_addr.bit.b0 /* KI0 input enable bit */
#define ki0pl kien_addr.bit.b1 /* KI0 input polarity select bit */
#define ki1en kien_addr.bit.b2 /* KI1 input enable bit */
#define ki1pl kien_addr.bit.b3 /* KI1 input polarity select bit */
#define ki2en kien_addr.bit.b4 /* KI2 input enable bit */
#define ki2pl kien_addr.bit.b5 /* KI2 input polarity select bit */
#define ki3en kien_addr.bit.b6 /* KI3 input enable bit */
#define ki3pl kien_addr.bit.b7 /* KI3 input polarity select bit */
/*------------------------------------------------------
Timer C control register0
------------------------------------------------------*/
union byte_def tcc0_addr;
#define tcc0 tcc0_addr.byte
#define tcc00 tcc0_addr.bit.b0 /* TimerC control bit */
#define tcc01 tcc0_addr.bit.b1 /* TimerC count source select bit */
#define tcc02 tcc0_addr.bit.b2 /* TimerC count source select bit */
#define tcc03 tcc0_addr.bit.b3 /* INT3 interrupt and capture polarity select bit */
#define tcc04 tcc0_addr.bit.b4 /* INT3 interrupt and capture polarity select bit */
#define tcc06 tcc0_addr.bit.b6 /* INT3 interrupt request generation timing select bit */
#define tcc07 tcc0_addr.bit.b7 /* INT3 interrupt/capture input switching bit */
/*------------------------------------------------------
Timer C control register1
------------------------------------------------------*/
union byte_def tcc1_addr;
#define tcc1 tcc1_addr.byte
#define tcc10 tcc1_addr.bit.b0 /* INT3 input filter select bit */
#define tcc11 tcc1_addr.bit.b1 /* INT3 input filter select bit */
#define tcc12 tcc1_addr.bit.b2 /* TimerC counter reload select bit */
#define tcc13 tcc1_addr.bit.b3 /* Compare0/capture select bit */
#define tcc14 tcc1_addr.bit.b4 /* Compare0 output mode select bit */
#define tcc15 tcc1_addr.bit.b5 /* Compare0 output mode select bit */
#define tcc16 tcc1_addr.bit.b6 /* Compare1 output mode select bit */
#define tcc17 tcc1_addr.bit.b7 /* Compare1 output mode select bit */
/*------------------------------------------------------
UART0 bit rate generator
------------------------------------------------------*/
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