stm32f10x_tim.txt

STM32手持式示波器源代码

000016  8920              LDRH     r0,[r4,#8]
000018  f4404080          ORR      r0,r0,#0x4000
00001c  8120              STRH     r0,[r4,#8]
;;;1104   }
00001e  bdf0              POP      {r4-r7,pc}
;;;1105   
                          ENDP


                          AREA ||i.TIM_ETRConfig||, CODE, READONLY, ALIGN=1

                  TIM_ETRConfig PROC
;;;1122     */
;;;1123   void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
000000  b530              PUSH     {r4,r5,lr}
;;;1124                      uint16_t ExtTRGFilter)
;;;1125   {
;;;1126     uint16_t tmpsmcr = 0;
000002  2400              MOVS     r4,#0
;;;1127     /* Check the parameters */
;;;1128     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1129     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1130     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1131     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1132     tmpsmcr = TIMx->SMCR;
000004  8904              LDRH     r4,[r0,#8]
;;;1133     /* Reset the ETR Bits */
;;;1134     tmpsmcr &= SMCR_ETR_Mask;
000006  b2e4              UXTB     r4,r4
;;;1135     /* Set the Prescaler, the Filter value and the Polarity */
;;;1136     tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
000008  061d              LSLS     r5,r3,#24
00000a  ea424515          ORR      r5,r2,r5,LSR #16
00000e  430d              ORRS     r5,r5,r1
000010  432c              ORRS     r4,r4,r5
;;;1137     /* Write to TIMx SMCR */
;;;1138     TIMx->SMCR = tmpsmcr;
000012  8104              STRH     r4,[r0,#8]
;;;1139   }
000014  bd30              POP      {r4,r5,pc}
;;;1140   
                          ENDP


                          AREA ||i.TIM_EncoderInterfaceConfig||, CODE, READONLY, ALIGN=1

                  TIM_EncoderInterfaceConfig PROC
;;;1238     */
;;;1239   void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
000000  b5f0              PUSH     {r4-r7,lr}
;;;1240                                   uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
;;;1241   {
;;;1242     uint16_t tmpsmcr = 0;
000002  2400              MOVS     r4,#0
;;;1243     uint16_t tmpccmr1 = 0;
000004  2500              MOVS     r5,#0
;;;1244     uint16_t tmpccer = 0;
000006  2600              MOVS     r6,#0
;;;1245       
;;;1246     /* Check the parameters */
;;;1247     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1248     assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
;;;1249     assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
;;;1250     assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
;;;1251   
;;;1252     /* Get the TIMx SMCR register value */
;;;1253     tmpsmcr = TIMx->SMCR;
000008  8904              LDRH     r4,[r0,#8]
;;;1254   
;;;1255     /* Get the TIMx CCMR1 register value */
;;;1256     tmpccmr1 = TIMx->CCMR1;
00000a  8b05              LDRH     r5,[r0,#0x18]
;;;1257   
;;;1258     /* Get the TIMx CCER register value */
;;;1259     tmpccer = TIMx->CCER;
00000c  8c06              LDRH     r6,[r0,#0x20]
;;;1260   
;;;1261     /* Set the encoder Mode */
;;;1262     tmpsmcr &= SMCR_SMS_Mask;
00000e  f64f77f8          MOV      r7,#0xfff8
000012  403c              ANDS     r4,r4,r7
;;;1263     tmpsmcr |= TIM_EncoderMode;
000014  430c              ORRS     r4,r4,r1
;;;1264   
;;;1265     /* Select the Capture Compare 1 and the Capture Compare 2 as input */
;;;1266     tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
000016  f64f47fc          MOV      r7,#0xfcfc
00001a  403d              ANDS     r5,r5,r7
;;;1267     tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
00001c  f2401701          MOV      r7,#0x101
000020  433d              ORRS     r5,r5,r7
;;;1268   
;;;1269     /* Set the TI1 and the TI2 Polarities */
;;;1270     tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset;
000022  f64f77dd          MOV      r7,#0xffdd
000026  403e              ANDS     r6,r6,r7
;;;1271     tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
000028  051f              LSLS     r7,r3,#20
00002a  ea424717          ORR      r7,r2,r7,LSR #16
00002e  433e              ORRS     r6,r6,r7
;;;1272   
;;;1273     /* Write to TIMx SMCR */
;;;1274     TIMx->SMCR = tmpsmcr;
000030  8104              STRH     r4,[r0,#8]
;;;1275   
;;;1276     /* Write to TIMx CCMR1 */
;;;1277     TIMx->CCMR1 = tmpccmr1;
000032  8305              STRH     r5,[r0,#0x18]
;;;1278   
;;;1279     /* Write to TIMx CCER */
;;;1280     TIMx->CCER = tmpccer;
000034  8406              STRH     r6,[r0,#0x20]
;;;1281   }
000036  bdf0              POP      {r4-r7,pc}
;;;1282   
                          ENDP


                          AREA ||i.TIM_ForcedOC1Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC1Config PROC
;;;1291     */
;;;1292   void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  2200              MOVS     r2,#0
;;;1293   {
;;;1294     uint16_t tmpccmr1 = 0;
;;;1295     /* Check the parameters */
;;;1296     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1297     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1298     tmpccmr1 = TIMx->CCMR1;
000002  8b02              LDRH     r2,[r0,#0x18]
;;;1299     /* Reset the OC1M Bits */
;;;1300     tmpccmr1 &= CCMR_OC13M_Mask;
000004  f64f738f          MOV      r3,#0xff8f
000008  401a              ANDS     r2,r2,r3
;;;1301     /* Configure The Forced output Mode */
;;;1302     tmpccmr1 |= TIM_ForcedAction;
00000a  430a              ORRS     r2,r2,r1
;;;1303     /* Write to TIMx CCMR1 register */
;;;1304     TIMx->CCMR1 = tmpccmr1;
00000c  8302              STRH     r2,[r0,#0x18]
;;;1305   }
00000e  4770              BX       lr
;;;1306   
                          ENDP


                          AREA ||i.TIM_ForcedOC2Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC2Config PROC
;;;1315     */
;;;1316   void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  2200              MOVS     r2,#0
;;;1317   {
;;;1318     uint16_t tmpccmr1 = 0;
;;;1319     /* Check the parameters */
;;;1320     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1321     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1322     tmpccmr1 = TIMx->CCMR1;
000002  8b02              LDRH     r2,[r0,#0x18]
;;;1323     /* Reset the OC2M Bits */
;;;1324     tmpccmr1 &= CCMR_OC24M_Mask;
000004  f64873ff          MOV      r3,#0x8fff
000008  401a              ANDS     r2,r2,r3
;;;1325     /* Configure The Forced output Mode */
;;;1326     tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
00000a  060b              LSLS     r3,r1,#24
00000c  ea424213          ORR      r2,r2,r3,LSR #16
;;;1327     /* Write to TIMx CCMR1 register */
;;;1328     TIMx->CCMR1 = tmpccmr1;
000010  8302              STRH     r2,[r0,#0x18]
;;;1329   }
000012  4770              BX       lr
;;;1330   
                          ENDP


                          AREA ||i.TIM_ForcedOC3Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC3Config PROC
;;;1339     */
;;;1340   void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  2200              MOVS     r2,#0
;;;1341   {
;;;1342     uint16_t tmpccmr2 = 0;
;;;1343     /* Check the parameters */
;;;1344     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1345     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1346     tmpccmr2 = TIMx->CCMR2;
000002  8b82              LDRH     r2,[r0,#0x1c]
;;;1347     /* Reset the OC1M Bits */
;;;1348     tmpccmr2 &= CCMR_OC13M_Mask;
000004  f64f738f          MOV      r3,#0xff8f
000008  401a              ANDS     r2,r2,r3
;;;1349     /* Configure The Forced output Mode */
;;;1350     tmpccmr2 |= TIM_ForcedAction;
00000a  430a              ORRS     r2,r2,r1
;;;1351     /* Write to TIMx CCMR2 register */
;;;1352     TIMx->CCMR2 = tmpccmr2;
00000c  8382              STRH     r2,[r0,#0x1c]
;;;1353   }
00000e  4770              BX       lr
;;;1354   
                          ENDP


                          AREA ||i.TIM_ForcedOC4Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC4Config PROC
;;;1363     */
;;;1364   void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  2200              MOVS     r2,#0
;;;1365   {
;;;1366     uint16_t tmpccmr2 = 0;
;;;1367     /* Check the parameters */
;;;1368     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1369     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1370     tmpccmr2 = TIMx->CCMR2;
000002  8b82              LDRH     r2,[r0,#0x1c]
;;;1371     /* Reset the OC2M Bits */
;;;1372     tmpccmr2 &= CCMR_OC24M_Mask;
000004  f64873ff          MOV      r3,#0x8fff
000008  401a              ANDS     r2,r2,r3
;;;1373     /* Configure The Forced output Mode */
;;;1374     tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
00000a  060b              LSLS     r3,r1,#24
00000c  ea424213          ORR      r2,r2,r3,LSR #16
;;;1375     /* Write to TIMx CCMR2 register */
;;;1376     TIMx->CCMR2 = tmpccmr2;
000010  8382              STRH     r2,[r0,#0x1c]
;;;1377   }
000012  4770              BX       lr
;;;1378   
                          ENDP


                          AREA ||i.TIM_GenerateEvent||, CODE, READONLY, ALIGN=1

                  TIM_GenerateEvent PROC
;;;886      */
;;;887    void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
000000  8281              STRH     r1,[r0,#0x14]
;;;888    { 
;;;889      /* Check the parameters */
;;;890      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;891      assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
;;;892      
;;;893      /* Set the event sources */
;;;894      TIMx->EGR = TIM_EventSource;
;;;895    }
000002  4770              BX       lr
;;;896    
                          ENDP


                          AREA ||i.TIM_GetCapture1||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture1 PROC
;;;2426     */
;;;2427   uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
000000  4601              MOV      r1,r0
;;;2428   {
;;;2429     /* Check the parameters */
;;;2430     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;2431     /* Get the Capture 1 Register value */
;;;2432     return TIMx->CCR1;
000002  8e88              LDRH     r0,[r1,#0x34]
;;;2433   }
000004  4770              BX       lr
;;;2434   
                          ENDP


                          AREA ||i.TIM_GetCapture2||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture2 PROC
;;;2439     */
;;;2440   uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
000000  4601              MOV      r1,r0
;;;2441   {
;;;2442     /* Check the parameters */
;;;2443     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;2444     /* Get the Capture 2 Register value */
;;;2445     return TIMx->CCR2;
000002  8f08              LDRH     r0,[r1,#0x38]
;;;2446   }
000004  4770              BX       lr
;;;2447   
                          ENDP


                          AREA ||i.TIM_GetCapture3||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture3 PROC
;;;2452     */
;;;2453   uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
000000  4601              MOV      r1,r0
;;;2454   {
;;;2455     /* Check the parameters */
;;;2456     assert_param(IS_TIM_123458_PERIPH(TIMx)); 
;;;2457     /* Get the Capture 3 Register value */
;;;2458     return TIMx->CCR3;
000002  8f88              LDRH     r0,[r1,#0x3c]
;;;2459   }
000004  4770              BX       lr
;;;2460   
                          ENDP


                          AREA ||i.TIM_GetCapture4||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture4 PROC
;;;2465     */
;;;2466   uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
000000  4601              MOV      r1,r0
;;;2467   {
;;;2468     /* Check the parameters */
;;;2469     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;2470     /* Get the Capture 4 Register value */
;;;2471     return TIMx->CCR4;
000002  f8b10040          LDRH     r0,[r1,#0x40]
;;;2472   }
000006  4770              BX       lr
;;;2473   
                          ENDP


                          AREA ||i.TIM_GetCounter||, CODE, READONLY, ALIGN=1