📄 stm32f10x_tim.txt
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;;;813 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
000000 b131 CBZ r1,|L19.16|
;;;814 {
;;;815 /* Check the parameters */
;;;816 assert_param(IS_TIM_18_PERIPH(TIMx));
;;;817 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;818 if (NewState != DISABLE)
;;;819 {
;;;820 /* Enable the TIM Main Output */
;;;821 TIMx->BDTR |= BDTR_MOE_Set;
000002 f8b02044 LDRH r2,[r0,#0x44]
000006 f4424200 ORR r2,r2,#0x8000
00000a f8a02044 STRH r2,[r0,#0x44]
00000e e005 B |L19.28|
|L19.16|
;;;822 }
;;;823 else
;;;824 {
;;;825 /* Disable the TIM Main Output */
;;;826 TIMx->BDTR &= BDTR_MOE_Reset;
000010 f8b02044 LDRH r2,[r0,#0x44]
000014 f3c2020e UBFX r2,r2,#0,#15
000018 f8a02044 STRH r2,[r0,#0x44]
|L19.28|
;;;827 }
;;;828 }
00001c 4770 BX lr
;;;829
ENDP
AREA ||i.TIM_DMACmd||, CODE, READONLY, ALIGN=1
TIM_DMACmd PROC
;;;939 */
;;;940 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
000000 b510 PUSH {r4,lr}
;;;941 {
;;;942 /* Check the parameters */
;;;943 assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;944 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
;;;945 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;946
;;;947 if (NewState != DISABLE)
000002 b11a CBZ r2,|L20.12|
;;;948 {
;;;949 /* Enable the DMA sources */
;;;950 TIMx->DIER |= TIM_DMASource;
000004 8983 LDRH r3,[r0,#0xc]
000006 430b ORRS r3,r3,r1
000008 8183 STRH r3,[r0,#0xc]
00000a e004 B |L20.22|
|L20.12|
;;;951 }
;;;952 else
;;;953 {
;;;954 /* Disable the DMA sources */
;;;955 TIMx->DIER &= (uint16_t)~TIM_DMASource;
00000c 8983 LDRH r3,[r0,#0xc]
00000e 43cc MVNS r4,r1
000010 b2a4 UXTH r4,r4
000012 4023 ANDS r3,r3,r4
000014 8183 STRH r3,[r0,#0xc]
|L20.22|
;;;956 }
;;;957 }
000016 bd10 POP {r4,pc}
;;;958
ENDP
AREA ||i.TIM_DMAConfig||, CODE, READONLY, ALIGN=1
TIM_DMAConfig PROC
;;;913 */
;;;914 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
000000 ea410302 ORR r3,r1,r2
;;;915 {
;;;916 /* Check the parameters */
;;;917 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;918 assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
;;;919 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
;;;920 /* Set the DMA Base and the DMA Burst Length */
;;;921 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
000004 f8a03048 STRH r3,[r0,#0x48]
;;;922 }
000008 4770 BX lr
;;;923
ENDP
AREA ||i.TIM_DeInit||, CODE, READONLY, ALIGN=2
TIM_DeInit PROC
;;;186 */
;;;187 void TIM_DeInit(TIM_TypeDef* TIMx)
000000 b510 PUSH {r4,lr}
;;;188 {
000002 4604 MOV r4,r0
;;;189 /* Check the parameters */
;;;190 assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;191
;;;192 if (TIMx == TIM1)
000004 482f LDR r0,|L22.196|
000006 4284 CMP r4,r0
000008 d108 BNE |L22.28|
;;;193 {
;;;194 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
00000a 2101 MOVS r1,#1
00000c 14c0 ASRS r0,r0,#19
00000e f7fffffe BL RCC_APB2PeriphResetCmd
;;;195 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
000012 2100 MOVS r1,#0
000014 14e0 ASRS r0,r4,#19
000016 f7fffffe BL RCC_APB2PeriphResetCmd
00001a e052 B |L22.194|
|L22.28|
;;;196 }
;;;197 else if (TIMx == TIM2)
00001c f1b44f80 CMP r4,#0x40000000
000020 d108 BNE |L22.52|
;;;198 {
;;;199 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
000022 2101 MOVS r1,#1
000024 4608 MOV r0,r1
000026 f7fffffe BL RCC_APB1PeriphResetCmd
;;;200 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
00002a 2100 MOVS r1,#0
00002c 2001 MOVS r0,#1
00002e f7fffffe BL RCC_APB1PeriphResetCmd
000032 e046 B |L22.194|
|L22.52|
;;;201 }
;;;202 else if (TIMx == TIM3)
000034 4824 LDR r0,|L22.200|
000036 4284 CMP r4,r0
000038 d108 BNE |L22.76|
;;;203 {
;;;204 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
00003a 2101 MOVS r1,#1
00003c 2002 MOVS r0,#2
00003e f7fffffe BL RCC_APB1PeriphResetCmd
;;;205 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
000042 2100 MOVS r1,#0
000044 2002 MOVS r0,#2
000046 f7fffffe BL RCC_APB1PeriphResetCmd
00004a e03a B |L22.194|
|L22.76|
;;;206 }
;;;207 else if (TIMx == TIM4)
00004c 481f LDR r0,|L22.204|
00004e 4284 CMP r4,r0
000050 d108 BNE |L22.100|
;;;208 {
;;;209 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
000052 2101 MOVS r1,#1
000054 2004 MOVS r0,#4
000056 f7fffffe BL RCC_APB1PeriphResetCmd
;;;210 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
00005a 2100 MOVS r1,#0
00005c 2004 MOVS r0,#4
00005e f7fffffe BL RCC_APB1PeriphResetCmd
000062 e02e B |L22.194|
|L22.100|
;;;211 }
;;;212 else if (TIMx == TIM5)
000064 481a LDR r0,|L22.208|
000066 4284 CMP r4,r0
000068 d108 BNE |L22.124|
;;;213 {
;;;214 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
00006a 2101 MOVS r1,#1
00006c 2008 MOVS r0,#8
00006e f7fffffe BL RCC_APB1PeriphResetCmd
;;;215 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
000072 2100 MOVS r1,#0
000074 2008 MOVS r0,#8
000076 f7fffffe BL RCC_APB1PeriphResetCmd
00007a e022 B |L22.194|
|L22.124|
;;;216 }
;;;217 else if (TIMx == TIM6)
00007c 4815 LDR r0,|L22.212|
00007e 4284 CMP r4,r0
000080 d108 BNE |L22.148|
;;;218 {
;;;219 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
000082 2101 MOVS r1,#1
000084 2010 MOVS r0,#0x10
000086 f7fffffe BL RCC_APB1PeriphResetCmd
;;;220 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
00008a 2100 MOVS r1,#0
00008c 2010 MOVS r0,#0x10
00008e f7fffffe BL RCC_APB1PeriphResetCmd
000092 e016 B |L22.194|
|L22.148|
;;;221 }
;;;222 else if (TIMx == TIM7)
000094 4810 LDR r0,|L22.216|
000096 4284 CMP r4,r0
000098 d108 BNE |L22.172|
;;;223 {
;;;224 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
00009a 2101 MOVS r1,#1
00009c 2020 MOVS r0,#0x20
00009e f7fffffe BL RCC_APB1PeriphResetCmd
;;;225 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
0000a2 2100 MOVS r1,#0
0000a4 2020 MOVS r0,#0x20
0000a6 f7fffffe BL RCC_APB1PeriphResetCmd
0000aa e00a B |L22.194|
|L22.172|
;;;226 }
;;;227 else
;;;228 {
;;;229 if (TIMx == TIM8)
0000ac 480b LDR r0,|L22.220|
0000ae 4284 CMP r4,r0
0000b0 d107 BNE |L22.194|
;;;230 {
;;;231 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
0000b2 2101 MOVS r1,#1
0000b4 1440 ASRS r0,r0,#17
0000b6 f7fffffe BL RCC_APB2PeriphResetCmd
;;;232 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
0000ba 2100 MOVS r1,#0
0000bc 1460 ASRS r0,r4,#17
0000be f7fffffe BL RCC_APB2PeriphResetCmd
|L22.194|
;;;233 }
;;;234 }
;;;235 }
0000c2 bd10 POP {r4,pc}
;;;236
ENDP
|L22.196|
DCD 0x40012c00
|L22.200|
DCD 0x40000400
|L22.204|
DCD 0x40000800
|L22.208|
DCD 0x40000c00
|L22.212|
DCD 0x40001000
|L22.216|
DCD 0x40001400
|L22.220|
DCD 0x40013400
AREA ||i.TIM_ETRClockMode1Config||, CODE, READONLY, ALIGN=1
TIM_ETRClockMode1Config PROC
;;;1049 */
;;;1050 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
000000 e92d41f0 PUSH {r4-r8,lr}
;;;1051 uint16_t ExtTRGFilter)
;;;1052 {
000004 4604 MOV r4,r0
000006 460d MOV r5,r1
000008 4616 MOV r6,r2
00000a 4698 MOV r8,r3
;;;1053 uint16_t tmpsmcr = 0;
00000c 2700 MOVS r7,#0
;;;1054 /* Check the parameters */
;;;1055 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1056 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1057 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1058 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1059 /* Configure the ETR Clock source */
;;;1060 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
00000e 4643 MOV r3,r8
000010 4632 MOV r2,r6
000012 4629 MOV r1,r5
000014 4620 MOV r0,r4
000016 f7fffffe BL TIM_ETRConfig
;;;1061
;;;1062 /* Get the TIMx SMCR register value */
;;;1063 tmpsmcr = TIMx->SMCR;
00001a 8927 LDRH r7,[r4,#8]
;;;1064 /* Reset the SMS Bits */
;;;1065 tmpsmcr &= SMCR_SMS_Mask;
00001c f64f70f8 MOV r0,#0xfff8
000020 4007 ANDS r7,r7,r0
;;;1066 /* Select the External clock mode1 */
;;;1067 tmpsmcr |= TIM_SlaveMode_External1;
000022 f0470707 ORR r7,r7,#7
;;;1068 /* Select the Trigger selection : ETRF */
;;;1069 tmpsmcr &= SMCR_TS_Mask;
000026 f64f708f MOV r0,#0xff8f
00002a 4007 ANDS r7,r7,r0
;;;1070 tmpsmcr |= TIM_TS_ETRF;
00002c f0470770 ORR r7,r7,#0x70
;;;1071 /* Write to TIMx SMCR */
;;;1072 TIMx->SMCR = tmpsmcr;
000030 8127 STRH r7,[r4,#8]
;;;1073 }
000032 e8bd81f0 POP {r4-r8,pc}
;;;1074
ENDP
AREA ||i.TIM_ETRClockMode2Config||, CODE, READONLY, ALIGN=1
TIM_ETRClockMode2Config PROC
;;;1091 */
;;;1092 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
000000 b5f0 PUSH {r4-r7,lr}
;;;1093 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
;;;1094 {
000002 4604 MOV r4,r0
000004 460d MOV r5,r1
000006 4616 MOV r6,r2
000008 461f MOV r7,r3
;;;1095 /* Check the parameters */
;;;1096 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1097 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1098 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1099 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1100 /* Configure the ETR Clock source */
;;;1101 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
00000a 463b MOV r3,r7
00000c 4632 MOV r2,r6
00000e 4629 MOV r1,r5
000010 4620 MOV r0,r4
000012 f7fffffe BL TIM_ETRConfig
;;;1102 /* Enable the External clock mode2 */
;;;1103 TIMx->SMCR |= SMCR_ECE_Set;
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