📄 stm32f10x_tim.txt
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000002 8882 LDRH r2,[r0,#4]
000004 f0420201 ORR r2,r2,#1
000008 8082 STRH r2,[r0,#4]
00000a e004 B |L8.22|
|L8.12|
;;;1467 }
;;;1468 else
;;;1469 {
;;;1470 /* Reset the CCPC Bit */
;;;1471 TIMx->CR2 &= CR2_CCPC_Reset;
00000c 8882 LDRH r2,[r0,#4]
00000e f64f73fe MOV r3,#0xfffe
000012 401a ANDS r2,r2,r3
000014 8082 STRH r2,[r0,#4]
|L8.22|
;;;1472 }
;;;1473 }
000016 4770 BX lr
;;;1474
ENDP
AREA ||i.TIM_CCxCmd||, CODE, READONLY, ALIGN=1
TIM_CCxCmd PROC
;;;1944 */
;;;1945 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
000000 b530 PUSH {r4,r5,lr}
;;;1946 {
;;;1947 uint16_t tmp = 0;
000002 2300 MOVS r3,#0
;;;1948
;;;1949 /* Check the parameters */
;;;1950 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1951 assert_param(IS_TIM_CHANNEL(TIM_Channel));
;;;1952 assert_param(IS_TIM_CCX(TIM_CCx));
;;;1953
;;;1954 tmp = CCER_CCE_Set << TIM_Channel;
000004 2401 MOVS r4,#1
000006 408c LSLS r4,r4,r1
000008 b2a3 UXTH r3,r4
;;;1955
;;;1956 /* Reset the CCxE Bit */
;;;1957 TIMx->CCER &= (uint16_t)~ tmp;
00000a 8c04 LDRH r4,[r0,#0x20]
00000c 43dd MVNS r5,r3
00000e b2ad UXTH r5,r5
000010 402c ANDS r4,r4,r5
000012 8404 STRH r4,[r0,#0x20]
;;;1958
;;;1959 /* Set or reset the CCxE Bit */
;;;1960 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
000014 8c04 LDRH r4,[r0,#0x20]
000016 fa02f501 LSL r5,r2,r1
00001a b2ad UXTH r5,r5
00001c 432c ORRS r4,r4,r5
00001e 8404 STRH r4,[r0,#0x20]
;;;1961 }
000020 bd30 POP {r4,r5,pc}
;;;1962
ENDP
AREA ||i.TIM_CCxNCmd||, CODE, READONLY, ALIGN=1
TIM_CCxNCmd PROC
;;;1974 */
;;;1975 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
000000 b530 PUSH {r4,r5,lr}
;;;1976 {
;;;1977 uint16_t tmp = 0;
000002 2300 MOVS r3,#0
;;;1978
;;;1979 /* Check the parameters */
;;;1980 assert_param(IS_TIM_18_PERIPH(TIMx));
;;;1981 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
;;;1982 assert_param(IS_TIM_CCXN(TIM_CCxN));
;;;1983
;;;1984 tmp = CCER_CCNE_Set << TIM_Channel;
000004 2404 MOVS r4,#4
000006 408c LSLS r4,r4,r1
000008 b2a3 UXTH r3,r4
;;;1985
;;;1986 /* Reset the CCxNE Bit */
;;;1987 TIMx->CCER &= (uint16_t) ~tmp;
00000a 8c04 LDRH r4,[r0,#0x20]
00000c 43dd MVNS r5,r3
00000e b2ad UXTH r5,r5
000010 402c ANDS r4,r4,r5
000012 8404 STRH r4,[r0,#0x20]
;;;1988
;;;1989 /* Set or reset the CCxNE Bit */
;;;1990 TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
000014 8c04 LDRH r4,[r0,#0x20]
000016 fa02f501 LSL r5,r2,r1
00001a b2ad UXTH r5,r5
00001c 432c ORRS r4,r4,r5
00001e 8404 STRH r4,[r0,#0x20]
;;;1991 }
000020 bd30 POP {r4,r5,pc}
;;;1992
ENDP
AREA ||i.TIM_ClearFlag||, CODE, READONLY, ALIGN=1
TIM_ClearFlag PROC
;;;2561 */
;;;2562 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
000000 43ca MVNS r2,r1
;;;2563 {
;;;2564 /* Check the parameters */
;;;2565 assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2566 assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
;;;2567
;;;2568 /* Clear the flags */
;;;2569 TIMx->SR = (uint16_t)~TIM_FLAG;
000002 8202 STRH r2,[r0,#0x10]
;;;2570 }
000004 4770 BX lr
;;;2571
ENDP
AREA ||i.TIM_ClearITPendingBit||, CODE, READONLY, ALIGN=1
TIM_ClearITPendingBit PROC
;;;2629 */
;;;2630 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
000000 43ca MVNS r2,r1
;;;2631 {
;;;2632 /* Check the parameters */
;;;2633 assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2634 assert_param(IS_TIM_IT(TIM_IT));
;;;2635 /* Clear the IT pending Bit */
;;;2636 TIMx->SR = (uint16_t)~TIM_IT;
000002 8202 STRH r2,[r0,#0x10]
;;;2637 }
000004 4770 BX lr
;;;2638
ENDP
AREA ||i.TIM_ClearOC1Ref||, CODE, READONLY, ALIGN=1
TIM_ClearOC1Ref PROC
;;;1679 */
;;;1680 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000 2200 MOVS r2,#0
;;;1681 {
;;;1682 uint16_t tmpccmr1 = 0;
;;;1683 /* Check the parameters */
;;;1684 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1685 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1686 tmpccmr1 = TIMx->CCMR1;
000002 8b02 LDRH r2,[r0,#0x18]
;;;1687 /* Reset the OC1CE Bit */
;;;1688 tmpccmr1 &= CCMR_OC13CE_Reset;
000004 f64f737f MOV r3,#0xff7f
000008 401a ANDS r2,r2,r3
;;;1689 /* Enable or Disable the Output Compare Clear Bit */
;;;1690 tmpccmr1 |= TIM_OCClear;
00000a 430a ORRS r2,r2,r1
;;;1691 /* Write to TIMx CCMR1 register */
;;;1692 TIMx->CCMR1 = tmpccmr1;
00000c 8302 STRH r2,[r0,#0x18]
;;;1693 }
00000e 4770 BX lr
;;;1694
ENDP
AREA ||i.TIM_ClearOC2Ref||, CODE, READONLY, ALIGN=1
TIM_ClearOC2Ref PROC
;;;1703 */
;;;1704 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000 2200 MOVS r2,#0
;;;1705 {
;;;1706 uint16_t tmpccmr1 = 0;
;;;1707 /* Check the parameters */
;;;1708 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1709 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1710 tmpccmr1 = TIMx->CCMR1;
000002 8b02 LDRH r2,[r0,#0x18]
;;;1711 /* Reset the OC2CE Bit */
;;;1712 tmpccmr1 &= CCMR_OC24CE_Reset;
000004 f3c2020e UBFX r2,r2,#0,#15
;;;1713 /* Enable or Disable the Output Compare Clear Bit */
;;;1714 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
000008 060b LSLS r3,r1,#24
00000a ea424213 ORR r2,r2,r3,LSR #16
;;;1715 /* Write to TIMx CCMR1 register */
;;;1716 TIMx->CCMR1 = tmpccmr1;
00000e 8302 STRH r2,[r0,#0x18]
;;;1717 }
000010 4770 BX lr
;;;1718
ENDP
AREA ||i.TIM_ClearOC3Ref||, CODE, READONLY, ALIGN=1
TIM_ClearOC3Ref PROC
;;;1727 */
;;;1728 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000 2200 MOVS r2,#0
;;;1729 {
;;;1730 uint16_t tmpccmr2 = 0;
;;;1731 /* Check the parameters */
;;;1732 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1733 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1734 tmpccmr2 = TIMx->CCMR2;
000002 8b82 LDRH r2,[r0,#0x1c]
;;;1735 /* Reset the OC3CE Bit */
;;;1736 tmpccmr2 &= CCMR_OC13CE_Reset;
000004 f64f737f MOV r3,#0xff7f
000008 401a ANDS r2,r2,r3
;;;1737 /* Enable or Disable the Output Compare Clear Bit */
;;;1738 tmpccmr2 |= TIM_OCClear;
00000a 430a ORRS r2,r2,r1
;;;1739 /* Write to TIMx CCMR2 register */
;;;1740 TIMx->CCMR2 = tmpccmr2;
00000c 8382 STRH r2,[r0,#0x1c]
;;;1741 }
00000e 4770 BX lr
;;;1742
ENDP
AREA ||i.TIM_ClearOC4Ref||, CODE, READONLY, ALIGN=1
TIM_ClearOC4Ref PROC
;;;1751 */
;;;1752 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000 2200 MOVS r2,#0
;;;1753 {
;;;1754 uint16_t tmpccmr2 = 0;
;;;1755 /* Check the parameters */
;;;1756 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1757 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1758 tmpccmr2 = TIMx->CCMR2;
000002 8b82 LDRH r2,[r0,#0x1c]
;;;1759 /* Reset the OC4CE Bit */
;;;1760 tmpccmr2 &= CCMR_OC24CE_Reset;
000004 f3c2020e UBFX r2,r2,#0,#15
;;;1761 /* Enable or Disable the Output Compare Clear Bit */
;;;1762 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
000008 060b LSLS r3,r1,#24
00000a ea424213 ORR r2,r2,r3,LSR #16
;;;1763 /* Write to TIMx CCMR2 register */
;;;1764 TIMx->CCMR2 = tmpccmr2;
00000e 8382 STRH r2,[r0,#0x1c]
;;;1765 }
000010 4770 BX lr
;;;1766
ENDP
AREA ||i.TIM_Cmd||, CODE, READONLY, ALIGN=1
TIM_Cmd PROC
;;;787 */
;;;788 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
000000 b121 CBZ r1,|L17.12|
;;;789 {
;;;790 /* Check the parameters */
;;;791 assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;792 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;793
;;;794 if (NewState != DISABLE)
;;;795 {
;;;796 /* Enable the TIM Counter */
;;;797 TIMx->CR1 |= CR1_CEN_Set;
000002 8802 LDRH r2,[r0,#0]
000004 f0420201 ORR r2,r2,#1
000008 8002 STRH r2,[r0,#0]
00000a e004 B |L17.22|
|L17.12|
;;;798 }
;;;799 else
;;;800 {
;;;801 /* Disable the TIM Counter */
;;;802 TIMx->CR1 &= CR1_CEN_Reset;
00000c 8802 LDRH r2,[r0,#0]
00000e f24033fe MOV r3,#0x3fe
000012 401a ANDS r2,r2,r3
000014 8002 STRH r2,[r0,#0]
|L17.22|
;;;803 }
;;;804 }
000016 4770 BX lr
;;;805
ENDP
AREA ||i.TIM_CounterModeConfig||, CODE, READONLY, ALIGN=1
TIM_CounterModeConfig PROC
;;;1173 */
;;;1174 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
000000 2200 MOVS r2,#0
;;;1175 {
;;;1176 uint16_t tmpcr1 = 0;
;;;1177 /* Check the parameters */
;;;1178 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1179 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
;;;1180 tmpcr1 = TIMx->CR1;
000002 8802 LDRH r2,[r0,#0]
;;;1181 /* Reset the CMS and DIR Bits */
;;;1182 tmpcr1 &= CR1_CounterMode_Mask;
000004 f240338f MOV r3,#0x38f
000008 401a ANDS r2,r2,r3
;;;1183 /* Set the Counter Mode */
;;;1184 tmpcr1 |= TIM_CounterMode;
00000a 430a ORRS r2,r2,r1
;;;1185 /* Write to TIMx CR1 register */
;;;1186 TIMx->CR1 = tmpcr1;
00000c 8002 STRH r2,[r0,#0]
;;;1187 }
00000e 4770 BX lr
;;;1188
ENDP
AREA ||i.TIM_CtrlPWMOutputs||, CODE, READONLY, ALIGN=1
TIM_CtrlPWMOutputs PROC
;;;812 */
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