📄 stm32f10x_dac.txt
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;;;150 }
00002e bd30 POP {r4,r5,pc}
;;;151
ENDP
|L6.48|
DCD 0x40007400
|L6.52|
DCD 0x40007000
AREA ||i.DAC_SetChannel1Data||, CODE, READONLY, ALIGN=2
DAC_SetChannel1Data PROC
;;;316 */
;;;317 void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
000000 2200 MOVS r2,#0
;;;318 {
;;;319 __IO uint32_t tmp = 0;
;;;320
;;;321 /* Check the parameters */
;;;322 assert_param(IS_DAC_ALIGN(DAC_Align));
;;;323 assert_param(IS_DAC_DATA(Data));
;;;324
;;;325 tmp = (uint32_t)DAC_BASE;
000002 4a03 LDR r2,|L7.16|
;;;326 tmp += DHR12R1_Offset + DAC_Align;
000004 f1000308 ADD r3,r0,#8
000008 441a ADD r2,r2,r3
;;;327
;;;328 /* Set the DAC channel1 selected data holding register */
;;;329 *(__IO uint32_t *) tmp = Data;
00000a 6011 STR r1,[r2,#0]
;;;330 }
00000c 4770 BX lr
;;;331
ENDP
00000e 0000 DCW 0x0000
|L7.16|
DCD 0x40007400
AREA ||i.DAC_SetChannel2Data||, CODE, READONLY, ALIGN=2
DAC_SetChannel2Data PROC
;;;341 */
;;;342 void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
000000 2200 MOVS r2,#0
;;;343 {
;;;344 __IO uint32_t tmp = 0;
;;;345
;;;346 /* Check the parameters */
;;;347 assert_param(IS_DAC_ALIGN(DAC_Align));
;;;348 assert_param(IS_DAC_DATA(Data));
;;;349
;;;350 tmp = (uint32_t)DAC_BASE;
000002 4a03 LDR r2,|L8.16|
;;;351 tmp += DHR12R2_Offset + DAC_Align;
000004 f1000314 ADD r3,r0,#0x14
000008 441a ADD r2,r2,r3
;;;352
;;;353 /* Set the DAC channel2 selected data holding register */
;;;354 *(__IO uint32_t *)tmp = Data;
00000a 6011 STR r1,[r2,#0]
;;;355 }
00000c 4770 BX lr
;;;356
ENDP
00000e 0000 DCW 0x0000
|L8.16|
DCD 0x40007400
AREA ||i.DAC_SetDualChannelData||, CODE, READONLY, ALIGN=2
DAC_SetDualChannelData PROC
;;;370 */
;;;371 void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
000000 b530 PUSH {r4,r5,lr}
;;;372 {
;;;373 uint32_t data = 0, tmp = 0;
000002 2300 MOVS r3,#0
000004 2400 MOVS r4,#0
;;;374
;;;375 /* Check the parameters */
;;;376 assert_param(IS_DAC_ALIGN(DAC_Align));
;;;377 assert_param(IS_DAC_DATA(Data1));
;;;378 assert_param(IS_DAC_DATA(Data2));
;;;379
;;;380 /* Calculate and set dual DAC data holding register value */
;;;381 if (DAC_Align == DAC_Align_8b_R)
000006 2808 CMP r0,#8
000008 d102 BNE |L9.16|
;;;382 {
;;;383 data = ((uint32_t)Data2 << 8) | Data1;
00000a ea422301 ORR r3,r2,r1,LSL #8
00000e e001 B |L9.20|
|L9.16|
;;;384 }
;;;385 else
;;;386 {
;;;387 data = ((uint32_t)Data2 << 16) | Data1;
000010 ea424301 ORR r3,r2,r1,LSL #16
|L9.20|
;;;388 }
;;;389
;;;390 tmp = (uint32_t)DAC_BASE;
000014 4c02 LDR r4,|L9.32|
;;;391 tmp += DHR12RD_Offset + DAC_Align;
000016 f1000520 ADD r5,r0,#0x20
00001a 442c ADD r4,r4,r5
;;;392
;;;393 /* Set the dual DAC selected data holding register */
;;;394 *(__IO uint32_t *)tmp = data;
00001c 6023 STR r3,[r4,#0]
;;;395 }
00001e bd30 POP {r4,r5,pc}
;;;396
ENDP
|L9.32|
DCD 0x40007400
AREA ||i.DAC_SoftwareTriggerCmd||, CODE, READONLY, ALIGN=2
DAC_SoftwareTriggerCmd PROC
;;;234 */
;;;235 void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
000000 b510 PUSH {r4,lr}
;;;236 {
;;;237 /* Check the parameters */
;;;238 assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;239 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;240 if (NewState != DISABLE)
000002 b149 CBZ r1,|L10.24|
;;;241 {
;;;242 /* Enable software trigger for the selected DAC channel */
;;;243 DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);
000004 4a09 LDR r2,|L10.44|
000006 6813 LDR r3,[r2,#0]
000008 0904 LSRS r4,r0,#4
00000a 2201 MOVS r2,#1
00000c 40a2 LSLS r2,r2,r4
00000e 4313 ORRS r3,r3,r2
000010 4a07 LDR r2,|L10.48|
000012 f8c23404 STR r3,[r2,#0x404]
000016 e008 B |L10.42|
|L10.24|
;;;244 }
;;;245 else
;;;246 {
;;;247 /* Disable software trigger for the selected DAC channel */
;;;248 DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));
000018 4a04 LDR r2,|L10.44|
00001a 6812 LDR r2,[r2,#0]
00001c 0904 LSRS r4,r0,#4
00001e 2301 MOVS r3,#1
000020 40a3 LSLS r3,r3,r4
000022 439a BICS r2,r2,r3
000024 4b02 LDR r3,|L10.48|
000026 f8c32404 STR r2,[r3,#0x404]
|L10.42|
;;;249 }
;;;250 }
00002a bd10 POP {r4,pc}
;;;251
ENDP
|L10.44|
DCD 0x40007404
|L10.48|
DCD 0x40007000
AREA ||i.DAC_StructInit||, CODE, READONLY, ALIGN=1
DAC_StructInit PROC
;;;157 */
;;;158 void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
000000 2100 MOVS r1,#0
;;;159 {
;;;160 /*--------------- Reset DAC init structure parameters values -----------------*/
;;;161 /* Initialize the DAC_Trigger member */
;;;162 DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
000002 6001 STR r1,[r0,#0]
;;;163 /* Initialize the DAC_WaveGeneration member */
;;;164 DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
000004 6041 STR r1,[r0,#4]
;;;165 /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
;;;166 DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
000006 6081 STR r1,[r0,#8]
;;;167 /* Initialize the DAC_OutputBuffer member */
;;;168 DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
000008 60c1 STR r1,[r0,#0xc]
;;;169 }
00000a 4770 BX lr
;;;170
ENDP
AREA ||i.DAC_WaveGenerationCmd||, CODE, READONLY, ALIGN=2
DAC_WaveGenerationCmd PROC
;;;288 */
;;;289 void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
000000 b510 PUSH {r4,lr}
;;;290 {
;;;291 /* Check the parameters */
;;;292 assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;293 assert_param(IS_DAC_WAVE(DAC_Wave));
;;;294 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;295 if (NewState != DISABLE)
000002 b142 CBZ r2,|L12.22|
;;;296 {
;;;297 /* Enable the selected wave generation for the selected DAC channel */
;;;298 DAC->CR |= DAC_Wave << DAC_Channel;
000004 4b08 LDR r3,|L12.40|
000006 681b LDR r3,[r3,#0]
000008 fa01f400 LSL r4,r1,r0
00000c 4323 ORRS r3,r3,r4
00000e 4c07 LDR r4,|L12.44|
000010 f8c43400 STR r3,[r4,#0x400]
000014 e007 B |L12.38|
|L12.22|
;;;299 }
;;;300 else
;;;301 {
;;;302 /* Disable the selected wave generation for the selected DAC channel */
;;;303 DAC->CR &= ~(DAC_Wave << DAC_Channel);
000016 4b04 LDR r3,|L12.40|
000018 681b LDR r3,[r3,#0]
00001a fa01f400 LSL r4,r1,r0
00001e 43a3 BICS r3,r3,r4
000020 4c02 LDR r4,|L12.44|
000022 f8c43400 STR r3,[r4,#0x400]
|L12.38|
;;;304 }
;;;305 }
000026 bd10 POP {r4,pc}
;;;306
ENDP
|L12.40|
DCD 0x40007400
|L12.44|
DCD 0x40007000
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