📄 stm32f10x_dac.txt
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; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_dac.o --depend=.\Obj\stm32f10x_dac.d --device=DARMSTM --apcs=interwork -O0 -Otime -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Source\inc -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c]
THUMB
AREA ||i.DAC_Cmd||, CODE, READONLY, ALIGN=2
DAC_Cmd PROC
;;;180 */
;;;181 void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
000000 b141 CBZ r1,|L1.20|
;;;182 {
;;;183 /* Check the parameters */
;;;184 assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;185 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;186 if (NewState != DISABLE)
;;;187 {
;;;188 /* Enable the selected DAC channel */
;;;189 DAC->CR |= CR_EN_Set << DAC_Channel;
000002 4a09 LDR r2,|L1.40|
000004 6813 LDR r3,[r2,#0]
000006 2201 MOVS r2,#1
000008 4082 LSLS r2,r2,r0
00000a 4313 ORRS r3,r3,r2
00000c 4a07 LDR r2,|L1.44|
00000e f8c23400 STR r3,[r2,#0x400]
000012 e007 B |L1.36|
|L1.20|
;;;190 }
;;;191 else
;;;192 {
;;;193 /* Disable the selected DAC channel */
;;;194 DAC->CR &= ~(CR_EN_Set << DAC_Channel);
000014 4a04 LDR r2,|L1.40|
000016 6813 LDR r3,[r2,#0]
000018 2201 MOVS r2,#1
00001a 4082 LSLS r2,r2,r0
00001c 4393 BICS r3,r3,r2
00001e 4a03 LDR r2,|L1.44|
000020 f8c23400 STR r3,[r2,#0x400]
|L1.36|
;;;195 }
;;;196 }
000024 4770 BX lr
;;;197
ENDP
000026 0000 DCW 0x0000
|L1.40|
DCD 0x40007400
|L1.44|
DCD 0x40007000
AREA ||i.DAC_DMACmd||, CODE, READONLY, ALIGN=2
DAC_DMACmd PROC
;;;207 */
;;;208 void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
000000 b141 CBZ r1,|L2.20|
;;;209 {
;;;210 /* Check the parameters */
;;;211 assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;212 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;213 if (NewState != DISABLE)
;;;214 {
;;;215 /* Enable the selected DAC channel DMA request */
;;;216 DAC->CR |= CR_DMAEN_Set << DAC_Channel;
000002 4a09 LDR r2,|L2.40|
000004 6813 LDR r3,[r2,#0]
000006 1492 ASRS r2,r2,#18
000008 4082 LSLS r2,r2,r0
00000a 4313 ORRS r3,r3,r2
00000c 4a07 LDR r2,|L2.44|
00000e f8c23400 STR r3,[r2,#0x400]
000012 e007 B |L2.36|
|L2.20|
;;;217 }
;;;218 else
;;;219 {
;;;220 /* Disable the selected DAC channel DMA request */
;;;221 DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);
000014 4a04 LDR r2,|L2.40|
000016 6813 LDR r3,[r2,#0]
000018 1492 ASRS r2,r2,#18
00001a 4082 LSLS r2,r2,r0
00001c 4393 BICS r3,r3,r2
00001e 4a03 LDR r2,|L2.44|
000020 f8c23400 STR r3,[r2,#0x400]
|L2.36|
;;;222 }
;;;223 }
000024 4770 BX lr
;;;224
ENDP
000026 0000 DCW 0x0000
|L2.40|
DCD 0x40007400
|L2.44|
DCD 0x40007000
AREA ||i.DAC_DeInit||, CODE, READONLY, ALIGN=1
DAC_DeInit PROC
;;;105 */
;;;106 void DAC_DeInit(void)
000000 b510 PUSH {r4,lr}
;;;107 {
;;;108 /* Enable DAC reset state */
;;;109 RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
000002 2101 MOVS r1,#1
000004 0748 LSLS r0,r1,#29
000006 f7fffffe BL RCC_APB1PeriphResetCmd
;;;110 /* Release DAC from reset state */
;;;111 RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
00000a 2100 MOVS r1,#0
00000c f04f5000 MOV r0,#0x20000000
000010 f7fffffe BL RCC_APB1PeriphResetCmd
;;;112 }
000014 bd10 POP {r4,pc}
;;;113
ENDP
AREA ||i.DAC_DualSoftwareTriggerCmd||, CODE, READONLY, ALIGN=2
DAC_DualSoftwareTriggerCmd PROC
;;;258 */
;;;259 void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
000000 b138 CBZ r0,|L4.18|
;;;260 {
;;;261 /* Check the parameters */
;;;262 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;263 if (NewState != DISABLE)
;;;264 {
;;;265 /* Enable software trigger for both DAC channels */
;;;266 DAC->SWTRIGR |= DUAL_SWTRIG_Set ;
000002 4908 LDR r1,|L4.36|
000004 6809 LDR r1,[r1,#0]
000006 f0410103 ORR r1,r1,#3
00000a 4a07 LDR r2,|L4.40|
00000c f8c21404 STR r1,[r2,#0x404]
000010 e006 B |L4.32|
|L4.18|
;;;267 }
;;;268 else
;;;269 {
;;;270 /* Disable software trigger for both DAC channels */
;;;271 DAC->SWTRIGR &= DUAL_SWTRIG_Reset;
000012 4904 LDR r1,|L4.36|
000014 6809 LDR r1,[r1,#0]
000016 f0210103 BIC r1,r1,#3
00001a 4a03 LDR r2,|L4.40|
00001c f8c21404 STR r1,[r2,#0x404]
|L4.32|
;;;272 }
;;;273 }
000020 4770 BX lr
;;;274
ENDP
000022 0000 DCW 0x0000
|L4.36|
DCD 0x40007404
|L4.40|
DCD 0x40007000
AREA ||i.DAC_GetDataOutputValue||, CODE, READONLY, ALIGN=2
DAC_GetDataOutputValue PROC
;;;404 */
;;;405 uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
000000 4601 MOV r1,r0
;;;406 {
;;;407 __IO uint32_t tmp = 0;
000002 2200 MOVS r2,#0
;;;408
;;;409 /* Check the parameters */
;;;410 assert_param(IS_DAC_CHANNEL(DAC_Channel));
;;;411
;;;412 tmp = (uint32_t) DAC_BASE ;
000004 4a03 LDR r2,|L5.20|
;;;413 tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2);
000006 202c MOVS r0,#0x2c
000008 eb000091 ADD r0,r0,r1,LSR #2
00000c 4402 ADD r2,r2,r0
;;;414
;;;415 /* Returns the DAC channel data output register value */
;;;416 return (uint16_t) (*(__IO uint32_t*) tmp);
00000e 6810 LDR r0,[r2,#0]
000010 b280 UXTH r0,r0
;;;417 }
000012 4770 BX lr
;;;418
ENDP
|L5.20|
DCD 0x40007400
AREA ||i.DAC_Init||, CODE, READONLY, ALIGN=2
DAC_Init PROC
;;;124 */
;;;125 void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
000000 b530 PUSH {r4,r5,lr}
;;;126 {
;;;127 uint32_t tmpreg1 = 0, tmpreg2 = 0;
000002 2200 MOVS r2,#0
000004 2300 MOVS r3,#0
;;;128 /* Check the DAC parameters */
;;;129 assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
;;;130 assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
;;;131 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
;;;132 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
;;;133 /*---------------------------- DAC CR Configuration --------------------------*/
;;;134 /* Get the DAC CR value */
;;;135 tmpreg1 = DAC->CR;
000006 4c0a LDR r4,|L6.48|
000008 6822 LDR r2,[r4,#0]
;;;136 /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
;;;137 tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);
00000a f64074fe MOV r4,#0xffe
00000e 4084 LSLS r4,r4,r0
000010 43a2 BICS r2,r2,r4
;;;138 /* Configure for the selected DAC channel: buffer output, trigger, wave genration,
;;;139 mask/amplitude for wave genration */
;;;140 /* Set TSELx and TENx bits according to DAC_Trigger value */
;;;141 /* Set WAVEx bits according to DAC_WaveGeneration value */
;;;142 /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
;;;143 /* Set BOFFx bit according to DAC_OutputBuffer value */
;;;144 tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
000012 e9d14500 LDRD r4,r5,[r1,#0]
000016 432c ORRS r4,r4,r5
000018 688d LDR r5,[r1,#8]
00001a 432c ORRS r4,r4,r5
00001c 68cd LDR r5,[r1,#0xc]
00001e ea440305 ORR r3,r4,r5
;;;145 DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
;;;146 /* Calculate CR register value depending on DAC_Channel */
;;;147 tmpreg1 |= tmpreg2 << DAC_Channel;
000022 fa03f400 LSL r4,r3,r0
000026 4322 ORRS r2,r2,r4
;;;148 /* Write to DAC CR */
;;;149 DAC->CR = tmpreg1;
000028 4c02 LDR r4,|L6.52|
00002a f8c42400 STR r2,[r4,#0x400]
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