📄 stm32f10x_usart.txt
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;;;145 else
;;;146 {
;;;147 if (USARTx == UART5)
00006c 480a LDR r0,|L7.152|
00006e 4284 CMP r4,r0
000070 d108 BNE |L7.132|
;;;148 {
;;;149 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
000072 2101 MOVS r1,#1
000074 0508 LSLS r0,r1,#20
000076 f7fffffe BL RCC_APB1PeriphResetCmd
;;;150 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
00007a 2100 MOVS r1,#0
00007c f44f1080 MOV r0,#0x100000
000080 f7fffffe BL RCC_APB1PeriphResetCmd
|L7.132|
;;;151 }
;;;152 }
;;;153 }
000084 bd10 POP {r4,pc}
;;;154
ENDP
000086 0000 DCW 0x0000
|L7.136|
DCD 0x40013800
|L7.140|
DCD 0x40004400
|L7.144|
DCD 0x40004800
|L7.148|
DCD 0x40004c00
|L7.152|
DCD 0x40005000
AREA ||i.USART_GetFlagStatus||, CODE, READONLY, ALIGN=1
USART_GetFlagStatus PROC
;;;782 */
;;;783 FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
000000 4602 MOV r2,r0
;;;784 {
;;;785 FlagStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;786 /* Check the parameters */
;;;787 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;788 assert_param(IS_USART_FLAG(USART_FLAG));
;;;789 /* The CTS flag is not available for UART4 and UART5 */
;;;790 if (USART_FLAG == USART_FLAG_CTS)
000004 f5b17f00 CMP r1,#0x200
000008 d100 BNE |L8.12|
;;;791 {
;;;792 assert_param(IS_USART_123_PERIPH(USARTx));
00000a bf00 NOP
|L8.12|
;;;793 }
;;;794
;;;795 if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
00000c 8813 LDRH r3,[r2,#0]
00000e 420b TST r3,r1
000010 d001 BEQ |L8.22|
;;;796 {
;;;797 bitstatus = SET;
000012 2001 MOVS r0,#1
000014 e000 B |L8.24|
|L8.22|
;;;798 }
;;;799 else
;;;800 {
;;;801 bitstatus = RESET;
000016 2000 MOVS r0,#0
|L8.24|
;;;802 }
;;;803 return bitstatus;
;;;804 }
000018 4770 BX lr
;;;805
ENDP
AREA ||i.USART_GetITStatus||, CODE, READONLY, ALIGN=1
USART_GetITStatus PROC
;;;864 */
;;;865 ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
000000 b570 PUSH {r4-r6,lr}
;;;866 {
000002 4602 MOV r2,r0
;;;867 uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
000004 2300 MOVS r3,#0
000006 2400 MOVS r4,#0
000008 2500 MOVS r5,#0
;;;868 ITStatus bitstatus = RESET;
00000a 2000 MOVS r0,#0
;;;869 /* Check the parameters */
;;;870 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;871 assert_param(IS_USART_GET_IT(USART_IT));
;;;872 /* The CTS interrupt is not available for UART4 and UART5 */
;;;873 if (USART_IT == USART_IT_CTS)
00000c f5a16610 SUB r6,r1,#0x900
000010 3e6a SUBS r6,r6,#0x6a
000012 d100 BNE |L9.22|
;;;874 {
;;;875 assert_param(IS_USART_123_PERIPH(USARTx));
000014 bf00 NOP
|L9.22|
;;;876 }
;;;877
;;;878 /* Get the USART register index */
;;;879 usartreg = (((uint8_t)USART_IT) >> 0x05);
000016 f3c11542 UBFX r5,r1,#5,#3
;;;880 /* Get the interrupt position */
;;;881 itmask = USART_IT & IT_Mask;
00001a f001041f AND r4,r1,#0x1f
;;;882 itmask = (uint32_t)0x01 << itmask;
00001e 2601 MOVS r6,#1
000020 fa06f404 LSL r4,r6,r4
;;;883
;;;884 if (usartreg == 0x01) /* The IT is in CR1 register */
000024 2d01 CMP r5,#1
000026 d102 BNE |L9.46|
;;;885 {
;;;886 itmask &= USARTx->CR1;
000028 8996 LDRH r6,[r2,#0xc]
00002a 4034 ANDS r4,r4,r6
00002c e006 B |L9.60|
|L9.46|
;;;887 }
;;;888 else if (usartreg == 0x02) /* The IT is in CR2 register */
00002e 2d02 CMP r5,#2
000030 d102 BNE |L9.56|
;;;889 {
;;;890 itmask &= USARTx->CR2;
000032 8a16 LDRH r6,[r2,#0x10]
000034 4034 ANDS r4,r4,r6
000036 e001 B |L9.60|
|L9.56|
;;;891 }
;;;892 else /* The IT is in CR3 register */
;;;893 {
;;;894 itmask &= USARTx->CR3;
000038 8a96 LDRH r6,[r2,#0x14]
00003a 4034 ANDS r4,r4,r6
|L9.60|
;;;895 }
;;;896
;;;897 bitpos = USART_IT >> 0x08;
00003c 120b ASRS r3,r1,#8
;;;898 bitpos = (uint32_t)0x01 << bitpos;
00003e 2601 MOVS r6,#1
000040 fa06f303 LSL r3,r6,r3
;;;899 bitpos &= USARTx->SR;
000044 8816 LDRH r6,[r2,#0]
000046 4033 ANDS r3,r3,r6
;;;900 if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
000048 b114 CBZ r4,|L9.80|
00004a b10b CBZ r3,|L9.80|
;;;901 {
;;;902 bitstatus = SET;
00004c 2001 MOVS r0,#1
00004e e000 B |L9.82|
|L9.80|
;;;903 }
;;;904 else
;;;905 {
;;;906 bitstatus = RESET;
000050 2000 MOVS r0,#0
|L9.82|
;;;907 }
;;;908
;;;909 return bitstatus;
;;;910 }
000052 bd70 POP {r4-r6,pc}
;;;911
ENDP
AREA ||i.USART_HalfDuplexCmd||, CODE, READONLY, ALIGN=1
USART_HalfDuplexCmd PROC
;;;697 */
;;;698 void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
000000 b121 CBZ r1,|L10.12|
;;;699 {
;;;700 /* Check the parameters */
;;;701 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;702 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;703
;;;704 if (NewState != DISABLE)
;;;705 {
;;;706 /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
;;;707 USARTx->CR3 |= CR3_HDSEL_Set;
000002 8a82 LDRH r2,[r0,#0x14]
000004 f0420208 ORR r2,r2,#8
000008 8282 STRH r2,[r0,#0x14]
00000a e004 B |L10.22|
|L10.12|
;;;708 }
;;;709 else
;;;710 {
;;;711 /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
;;;712 USARTx->CR3 &= CR3_HDSEL_Reset;
00000c 8a82 LDRH r2,[r0,#0x14]
00000e f64f73f7 MOV r3,#0xfff7
000012 401a ANDS r2,r2,r3
000014 8282 STRH r2,[r0,#0x14]
|L10.22|
;;;713 }
;;;714 }
000016 4770 BX lr
;;;715
ENDP
AREA ||i.USART_ITConfig||, CODE, READONLY, ALIGN=1
USART_ITConfig PROC
;;;355 */
;;;356 void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
000000 b5f0 PUSH {r4-r7,lr}
;;;357 {
;;;358 uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
000002 2400 MOVS r4,#0
000004 2500 MOVS r5,#0
000006 2600 MOVS r6,#0
;;;359 uint32_t usartxbase = 0x00;
000008 2300 MOVS r3,#0
;;;360 /* Check the parameters */
;;;361 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;362 assert_param(IS_USART_CONFIG_IT(USART_IT));
;;;363 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;364 /* The CTS interrupt is not available for UART4 and UART5 */
;;;365 if (USART_IT == USART_IT_CTS)
00000a f5a16710 SUB r7,r1,#0x900
00000e 3f6a SUBS r7,r7,#0x6a
000010 d100 BNE |L11.20|
;;;366 {
;;;367 assert_param(IS_USART_123_PERIPH(USARTx));
000012 bf00 NOP
|L11.20|
;;;368 }
;;;369
;;;370 usartxbase = (uint32_t)USARTx;
000014 4603 MOV r3,r0
;;;371
;;;372 /* Get the USART register index */
;;;373 usartreg = (((uint8_t)USART_IT) >> 0x05);
000016 f3c11442 UBFX r4,r1,#5,#3
;;;374
;;;375 /* Get the interrupt position */
;;;376 itpos = USART_IT & IT_Mask;
00001a f001051f AND r5,r1,#0x1f
;;;377 itmask = (((uint32_t)0x01) << itpos);
00001e 2701 MOVS r7,#1
000020 fa07f605 LSL r6,r7,r5
;;;378
;;;379 if (usartreg == 0x01) /* The IT is in CR1 register */
000024 2c01 CMP r4,#1
000026 d101 BNE |L11.44|
;;;380 {
;;;381 usartxbase += 0x0C;
000028 330c ADDS r3,r3,#0xc
00002a e004 B |L11.54|
|L11.44|
;;;382 }
;;;383 else if (usartreg == 0x02) /* The IT is in CR2 register */
00002c 2c02 CMP r4,#2
00002e d101 BNE |L11.52|
;;;384 {
;;;385 usartxbase += 0x10;
000030 3310 ADDS r3,r3,#0x10
000032 e000 B |L11.54|
|L11.52|
;;;386 }
;;;387 else /* The IT is in CR3 register */
;;;388 {
;;;389 usartxbase += 0x14;
000034 3314 ADDS r3,r3,#0x14
|L11.54|
;;;390 }
;;;391 if (NewState != DISABLE)
000036 b11a CBZ r2,|L11.64|
;;;392 {
;;;393 *(__IO uint32_t*)usartxbase |= itmask;
000038 681f LDR r7,[r3,#0]
00003a 4337 ORRS r7,r7,r6
00003c 601f STR r7,[r3,#0]
00003e e002 B |L11.70|
|L11.64|
;;;394 }
;;;395 else
;;;396 {
;;;397 *(__IO uint32_t*)usartxbase &= ~itmask;
000040 681f LDR r7,[r3,#0]
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