stm32f10x_fsmc.txt
来自「STM32手持式示波器源代码」· 文本 代码 · 共 1,396 行 · 第 1/5 页
TXT
1,396 行
00003a 60d1 STR r1,[r2,#0xc]
;;;392 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
00003c 6b02 LDR r2,[r0,#0x30]
00003e 6111 STR r1,[r2,#0x10]
;;;393 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
000040 6b02 LDR r2,[r0,#0x30]
000042 6151 STR r1,[r2,#0x14]
;;;394 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
000044 2100 MOVS r1,#0
000046 6b02 LDR r2,[r0,#0x30]
000048 6191 STR r1,[r2,#0x18]
;;;395 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
00004a 210f MOVS r1,#0xf
00004c 6b42 LDR r2,[r0,#0x34]
00004e 6011 STR r1,[r2,#0]
;;;396 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
000050 6b42 LDR r2,[r0,#0x34]
000052 6051 STR r1,[r2,#4]
;;;397 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
000054 21ff MOVS r1,#0xff
000056 6b42 LDR r2,[r0,#0x34]
000058 6091 STR r1,[r2,#8]
;;;398 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
00005a 210f MOVS r1,#0xf
00005c 6b42 LDR r2,[r0,#0x34]
00005e 60d1 STR r1,[r2,#0xc]
;;;399 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
000060 6b42 LDR r2,[r0,#0x34]
000062 6111 STR r1,[r2,#0x10]
;;;400 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
000064 6b42 LDR r2,[r0,#0x34]
000066 6151 STR r1,[r2,#0x14]
;;;401 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
000068 2100 MOVS r1,#0
00006a 6b42 LDR r2,[r0,#0x34]
00006c 6191 STR r1,[r2,#0x18]
;;;402 }
00006e 4770 BX lr
;;;403
ENDP
AREA ||i.FSMC_PCCARDCmd||, CODE, READONLY, ALIGN=2
FSMC_PCCARDCmd PROC
;;;529 */
;;;530 void FSMC_PCCARDCmd(FunctionalState NewState)
000000 b140 CBZ r0,|L16.20|
;;;531 {
;;;532 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;533
;;;534 if (NewState != DISABLE)
;;;535 {
;;;536 /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
;;;537 FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
000002 4909 LDR r1,|L16.40|
000004 6809 LDR r1,[r1,#0]
000006 f0410104 ORR r1,r1,#4
00000a f04f4220 MOV r2,#0xa0000000
00000e f8c210a0 STR r1,[r2,#0xa0]
000012 e007 B |L16.36|
|L16.20|
;;;538 }
;;;539 else
;;;540 {
;;;541 /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
;;;542 FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
000014 4904 LDR r1,|L16.40|
000016 6809 LDR r1,[r1,#0]
000018 4a04 LDR r2,|L16.44|
00001a 4011 ANDS r1,r1,r2
00001c f04f4220 MOV r2,#0xa0000000
000020 f8c210a0 STR r1,[r2,#0xa0]
|L16.36|
;;;543 }
;;;544 }
000024 4770 BX lr
;;;545
ENDP
000026 0000 DCW 0x0000
|L16.40|
DCD 0xa00000a0
|L16.44|
DCD 0x000ffffb
AREA ||i.FSMC_PCCARDDeInit||, CODE, READONLY, ALIGN=2
FSMC_PCCARDDeInit PROC
;;;156 */
;;;157 void FSMC_PCCARDDeInit(void)
000000 2018 MOVS r0,#0x18
;;;158 {
;;;159 /* Set the FSMC_Bank4 registers to their reset values */
;;;160 FSMC_Bank4->PCR4 = 0x00000018;
000002 4908 LDR r1,|L17.36|
000004 6008 STR r0,[r1,#0]
;;;161 FSMC_Bank4->SR4 = 0x00000000;
000006 2000 MOVS r0,#0
000008 0609 LSLS r1,r1,#24
00000a f8c100a4 STR r0,[r1,#0xa4]
;;;162 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
00000e f04f30fc MOV r0,#0xfcfcfcfc
000012 4904 LDR r1,|L17.36|
000014 3108 ADDS r1,r1,#8
000016 6008 STR r0,[r1,#0]
;;;163 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
000018 1d09 ADDS r1,r1,#4
00001a 6008 STR r0,[r1,#0]
;;;164 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
00001c 1d09 ADDS r1,r1,#4
00001e 6008 STR r0,[r1,#0]
;;;165 }
000020 4770 BX lr
;;;166
ENDP
000022 0000 DCW 0x0000
|L17.36|
DCD 0xa00000a0
AREA ||i.FSMC_PCCARDInit||, CODE, READONLY, ALIGN=2
FSMC_PCCARDInit PROC
;;;320 */
;;;321 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
000000 6801 LDR r1,[r0,#0]
;;;322 {
;;;323 /* Check the parameters */
;;;324 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
;;;325 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
;;;326 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
;;;327
;;;328 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
;;;329 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
;;;330 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
;;;331 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
;;;332
;;;333 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
;;;334 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
;;;335 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
;;;336 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
;;;337 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
;;;338 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
;;;339 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
;;;340 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
;;;341
;;;342 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
;;;343 FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
000002 f0410110 ORR r1,r1,#0x10
000006 6842 LDR r2,[r0,#4]
000008 ea412142 ORR r1,r1,r2,LSL #9
00000c 6882 LDR r2,[r0,#8]
00000e ea413142 ORR r1,r1,r2,LSL #13
000012 4a1b LDR r2,|L18.128|
000014 6011 STR r1,[r2,#0]
;;;344 FSMC_MemoryDataWidth_16b |
;;;345 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
;;;346 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
;;;347
;;;348 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
;;;349 FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
000016 68c1 LDR r1,[r0,#0xc]
000018 6809 LDR r1,[r1,#0]
00001a 68c2 LDR r2,[r0,#0xc]
00001c 6852 LDR r2,[r2,#4]
00001e ea412102 ORR r1,r1,r2,LSL #8
000022 68c2 LDR r2,[r0,#0xc]
000024 6892 LDR r2,[r2,#8]
000026 ea414102 ORR r1,r1,r2,LSL #16
00002a 68c2 LDR r2,[r0,#0xc]
00002c 68d2 LDR r2,[r2,#0xc]
00002e ea416102 ORR r1,r1,r2,LSL #24
000032 4a13 LDR r2,|L18.128|
000034 3208 ADDS r2,r2,#8
000036 6011 STR r1,[r2,#0]
;;;350 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;351 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;352 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;353
;;;354 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
;;;355 FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
000038 6901 LDR r1,[r0,#0x10]
00003a 6809 LDR r1,[r1,#0]
00003c 6902 LDR r2,[r0,#0x10]
00003e 6852 LDR r2,[r2,#4]
000040 ea412102 ORR r1,r1,r2,LSL #8
000044 6902 LDR r2,[r0,#0x10]
000046 6892 LDR r2,[r2,#8]
000048 ea414102 ORR r1,r1,r2,LSL #16
00004c 6902 LDR r2,[r0,#0x10]
00004e 68d2 LDR r2,[r2,#0xc]
000050 ea416102 ORR r1,r1,r2,LSL #24
000054 4a0a LDR r2,|L18.128|
000056 320c ADDS r2,r2,#0xc
000058 6011 STR r1,[r2,#0]
;;;356 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;357 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;358 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;359
;;;360 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
;;;361 FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
00005a 6941 LDR r1,[r0,#0x14]
00005c 6809 LDR r1,[r1,#0]
00005e 6942 LDR r2,[r0,#0x14]
000060 6852 LDR r2,[r2,#4]
000062 ea412102 ORR r1,r1,r2,LSL #8
000066 6942 LDR r2,[r0,#0x14]
000068 6892 LDR r2,[r2,#8]
00006a ea414102 ORR r1,r1,r2,LSL #16
00006e 6942 LDR r2,[r0,#0x14]
000070 68d2 LDR r2,[r2,#0xc]
000072 ea416102 ORR r1,r1,r2,LSL #24
000076 f04f4220 MOV r2,#0xa0000000
00007a f8c210b0 STR r1,[r2,#0xb0]
;;;362 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;363 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;364 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;365 }
00007e 4770 BX lr
;;;366
ENDP
|L18.128|
DCD 0xa00000a0
AREA ||i.FSMC_PCCARDStructInit||, CODE, READONLY, ALIGN=1
FSMC_PCCARDStructInit PROC
;;;435 */
;;;436 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
000000 2100 MOVS r1,#0
;;;437 {
;;;438 /* Reset PCCARD Init structure parameters values */
;;;439 FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
000002 6001 STR r1,[r0,#0]
;;;440 FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
000004 6041 STR r1,[r0,#4]
;;;441 FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
000006 6081 STR r1,[r0,#8]
;;;442 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000008 21fc MOVS r1,#0xfc
00000a 68c2 LDR r2,[r0,#0xc]
00000c 6011 STR r1,[r2,#0]
;;;443 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00000e 68c2 LDR r2,[r0,#0xc]
000010 6051 STR r1,[r2,#4]
;;;444 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000012 68c2 LDR r2,[r0,#0xc]
000014 6091 STR r1,[r2,#8]
;;;445 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000016 68c2 LDR r2,[r0,#0xc]
000018 60d1 STR r1,[r2,#0xc]
;;;446 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00001a 6902 LDR r2,[r0,#0x10]
00001c 6011 STR r1,[r2,#0]
;;;447 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00001e 6902 LDR r2,[r0,#0x10]
000020 6051 STR r1,[r2,#4]
;;;448 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000022 6902 LDR r2,[r0,#0x10]
000024 6091 STR r1,[r2,#8]
;;;449 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000026 6902 LDR r2,[r0,#0x10]
000028 60d1 STR r1,[r2,#0xc]
;;;450 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00002a 6942 LDR r2,[r0,#0x14]
00002c 6011 STR r1,[r2,#0]
;;;451 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00002e 6942 LDR r2,[r0,#0x14]
000030 6051 STR r1,[r2,#4]
;;;452 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000032 6942 LDR r2,[r0,#0x14]
000034 6091 STR r1,[r2,#8]
;;;453 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000036 6942 LDR⌨️ 快捷键说明
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