stm32f10x_fsmc.txt
来自「STM32手持式示波器源代码」· 文本 代码 · 共 1,396 行 · 第 1/5 页
TXT
1,396 行
000022 401a ANDS r2,r2,r3
000024 f04f4320 MOV r3,#0xa0000000
000028 f8432020 STR r2,[r3,r0,LSL #2]
|L12.44|
;;;481 }
;;;482 }
00002c 4770 BX lr
;;;483
ENDP
00002e 0000 DCW 0x0000
|L12.48|
DCD 0x000ffffe
AREA ||i.FSMC_NORSRAMDeInit||, CODE, READONLY, ALIGN=1
FSMC_NORSRAMDeInit PROC
;;;100 */
;;;101 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
000000 b930 CBNZ r0,|L13.16|
;;;102 {
;;;103 /* Check the parameter */
;;;104 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
;;;105
;;;106 /* FSMC_Bank1_NORSRAM1 */
;;;107 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
;;;108 {
;;;109 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
000002 f24301db MOV r1,#0x30db
000006 f04f4220 MOV r2,#0xa0000000
00000a f8421020 STR r1,[r2,r0,LSL #2]
00000e e005 B |L13.28|
|L13.16|
;;;110 }
;;;111 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
;;;112 else
;;;113 {
;;;114 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
000010 f24301d2 MOV r1,#0x30d2
000014 f04f4220 MOV r2,#0xa0000000
000018 f8421020 STR r1,[r2,r0,LSL #2]
|L13.28|
;;;115 }
;;;116 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
00001c f06f4270 MVN r2,#0xf0000000
000020 1c41 ADDS r1,r0,#1
000022 f04f4320 MOV r3,#0xa0000000
000026 f8432021 STR r2,[r3,r1,LSL #2]
;;;117 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
00002a 4611 MOV r1,r2
00002c 461a MOV r2,r3
00002e eb020280 ADD r2,r2,r0,LSL #2
000032 f8c21104 STR r1,[r2,#0x104]
;;;118 }
000036 4770 BX lr
;;;119
ENDP
AREA ||i.FSMC_NORSRAMInit||, CODE, READONLY, ALIGN=1
FSMC_NORSRAMInit PROC
;;;174 */
;;;175 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
000000 e9d01201 LDRD r1,r2,[r0,#4]
;;;176 {
;;;177 /* Check the parameters */
;;;178 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
;;;179 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
;;;180 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
;;;181 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
;;;182 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
;;;183 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
;;;184 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
;;;185 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
;;;186 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
;;;187 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
;;;188 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
;;;189 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
;;;190 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
;;;191 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
;;;192 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
;;;193 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
;;;194 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
;;;195 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
;;;196 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
;;;197
;;;198 /* Bank1 NOR/SRAM control register configuration */
;;;199 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
000004 4311 ORRS r1,r1,r2
000006 68c2 LDR r2,[r0,#0xc]
000008 4311 ORRS r1,r1,r2
00000a 6902 LDR r2,[r0,#0x10]
00000c 4311 ORRS r1,r1,r2
00000e 6942 LDR r2,[r0,#0x14]
000010 4311 ORRS r1,r1,r2
000012 6982 LDR r2,[r0,#0x18]
000014 4311 ORRS r1,r1,r2
000016 69c2 LDR r2,[r0,#0x1c]
000018 4311 ORRS r1,r1,r2
00001a 6a02 LDR r2,[r0,#0x20]
00001c 4311 ORRS r1,r1,r2
00001e 6a42 LDR r2,[r0,#0x24]
000020 4311 ORRS r1,r1,r2
000022 6a82 LDR r2,[r0,#0x28]
000024 4311 ORRS r1,r1,r2
000026 6ac2 LDR r2,[r0,#0x2c]
000028 4311 ORRS r1,r1,r2
00002a f04f4320 MOV r3,#0xa0000000
00002e 6802 LDR r2,[r0,#0]
000030 f8431022 STR r1,[r3,r2,LSL #2]
;;;200 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
;;;201 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
;;;202 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
;;;203 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
;;;204 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
;;;205 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
;;;206 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
;;;207 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
;;;208 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
;;;209 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
;;;210 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
;;;211 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
000034 6881 LDR r1,[r0,#8]
000036 2908 CMP r1,#8
000038 d108 BNE |L14.76|
;;;212 {
;;;213 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
00003a 461a MOV r2,r3
00003c 6801 LDR r1,[r0,#0]
00003e f8521021 LDR r1,[r2,r1,LSL #2]
000042 f0410140 ORR r1,r1,#0x40
000046 6802 LDR r2,[r0,#0]
000048 f8431022 STR r1,[r3,r2,LSL #2]
|L14.76|
;;;214 }
;;;215 /* Bank1 NOR/SRAM timing register configuration */
;;;216 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
00004c 6b01 LDR r1,[r0,#0x30]
00004e 6809 LDR r1,[r1,#0]
000050 6b02 LDR r2,[r0,#0x30]
000052 6852 LDR r2,[r2,#4]
000054 ea411102 ORR r1,r1,r2,LSL #4
000058 6b02 LDR r2,[r0,#0x30]
00005a 6892 LDR r2,[r2,#8]
00005c ea412102 ORR r1,r1,r2,LSL #8
000060 6b02 LDR r2,[r0,#0x30]
000062 68d2 LDR r2,[r2,#0xc]
000064 ea414102 ORR r1,r1,r2,LSL #16
000068 6b02 LDR r2,[r0,#0x30]
00006a 6912 LDR r2,[r2,#0x10]
00006c ea415102 ORR r1,r1,r2,LSL #20
000070 6b02 LDR r2,[r0,#0x30]
000072 6952 LDR r2,[r2,#0x14]
000074 ea416202 ORR r2,r1,r2,LSL #24
000078 6b01 LDR r1,[r0,#0x30]
00007a 6989 LDR r1,[r1,#0x18]
00007c 430a ORRS r2,r2,r1
00007e 6801 LDR r1,[r0,#0]
000080 1c49 ADDS r1,r1,#1
000082 f04f4320 MOV r3,#0xa0000000
000086 f8432021 STR r2,[r3,r1,LSL #2]
;;;217 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
;;;218 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
;;;219 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
;;;220 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
;;;221 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
;;;222 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
;;;223 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
;;;224
;;;225
;;;226 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
;;;227 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
00008a 6a81 LDR r1,[r0,#0x28]
00008c f5b14f80 CMP r1,#0x4000
000090 d11a BNE |L14.200|
;;;228 {
;;;229 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
;;;230 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
;;;231 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
;;;232 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
;;;233 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
;;;234 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
;;;235 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
000092 6b41 LDR r1,[r0,#0x34]
000094 6809 LDR r1,[r1,#0]
000096 6b42 LDR r2,[r0,#0x34]
000098 6852 LDR r2,[r2,#4]
00009a ea411102 ORR r1,r1,r2,LSL #4
00009e 6b42 LDR r2,[r0,#0x34]
0000a0 6892 LDR r2,[r2,#8]
0000a2 ea412102 ORR r1,r1,r2,LSL #8
0000a6 6b42 LDR r2,[r0,#0x34]
0000a8 6912 LDR r2,[r2,#0x10]
0000aa ea415102 ORR r1,r1,r2,LSL #20
0000ae 6b42 LDR r2,[r0,#0x34]
0000b0 6952 LDR r2,[r2,#0x14]
0000b2 ea416102 ORR r1,r1,r2,LSL #24
0000b6 6b42 LDR r2,[r0,#0x34]
0000b8 6992 LDR r2,[r2,#0x18]
0000ba 4311 ORRS r1,r1,r2
0000bc 6802 LDR r2,[r0,#0]
0000be eb030282 ADD r2,r3,r2,LSL #2
0000c2 f8c21104 STR r1,[r2,#0x104]
0000c6 e008 B |L14.218|
|L14.200|
;;;236 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
;;;237 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
;;;238 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
;;;239 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
;;;240 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
;;;241 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
;;;242 }
;;;243 else
;;;244 {
;;;245 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
0000c8 f06f4170 MVN r1,#0xf0000000
0000cc f04f4320 MOV r3,#0xa0000000
0000d0 6802 LDR r2,[r0,#0]
0000d2 eb030282 ADD r2,r3,r2,LSL #2
0000d6 f8c21104 STR r1,[r2,#0x104]
|L14.218|
;;;246 }
;;;247 }
0000da 4770 BX lr
;;;248
ENDP
AREA ||i.FSMC_NORSRAMStructInit||, CODE, READONLY, ALIGN=1
FSMC_NORSRAMStructInit PROC
;;;372 */
;;;373 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
000000 2100 MOVS r1,#0
;;;374 {
;;;375 /* Reset NOR/SRAM Init structure parameters values */
;;;376 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
000002 6001 STR r1,[r0,#0]
;;;377 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
000004 2102 MOVS r1,#2
000006 6041 STR r1,[r0,#4]
;;;378 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
000008 2100 MOVS r1,#0
00000a 6081 STR r1,[r0,#8]
;;;379 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00000c 60c1 STR r1,[r0,#0xc]
;;;380 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00000e 6101 STR r1,[r0,#0x10]
;;;381 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
000010 6141 STR r1,[r0,#0x14]
;;;382 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
000012 6181 STR r1,[r0,#0x18]
;;;383 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
000014 61c1 STR r1,[r0,#0x1c]
;;;384 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
000016 f44f5180 MOV r1,#0x1000
00001a 6201 STR r1,[r0,#0x20]
;;;385 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
00001c 0049 LSLS r1,r1,#1
00001e 6241 STR r1,[r0,#0x24]
;;;386 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
000020 2100 MOVS r1,#0
000022 6281 STR r1,[r0,#0x28]
;;;387 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
000024 62c1 STR r1,[r0,#0x2c]
;;;388 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
000026 210f MOVS r1,#0xf
000028 6b02 LDR r2,[r0,#0x30]
00002a 6011 STR r1,[r2,#0]
;;;389 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
00002c 6b02 LDR r2,[r0,#0x30]
00002e 6051 STR r1,[r2,#4]
;;;390 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
000030 21ff MOVS r1,#0xff
000032 6b02 LDR r2,[r0,#0x30]
000034 6091 STR r1,[r2,#8]
;;;391 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
000036 210f MOVS r1,#0xf
000038 6b02 LDR r2,[r0,#0x30]
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