stm32f10x_fsmc.txt

来自「STM32手持式示波器源代码」· 文本 代码 · 共 1,396 行 · 第 1/5 页

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;;;556    void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
000000  b199              CBZ      r1,|L9.42|
;;;557    {
;;;558      assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;559      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;560      
;;;561      if (NewState != DISABLE)
;;;562      {
;;;563        /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
;;;564        if(FSMC_Bank == FSMC_Bank2_NAND)
000002  2810              CMP      r0,#0x10
000004  d108              BNE      |L9.24|
;;;565        {
;;;566          FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
000006  f04f4220          MOV      r2,#0xa0000000
00000a  6e12              LDR      r2,[r2,#0x60]
00000c  f0420240          ORR      r2,r2,#0x40
000010  f04f4320          MOV      r3,#0xa0000000
000014  661a              STR      r2,[r3,#0x60]
000016  e01b              B        |L9.80|
                  |L9.24|
;;;567        }
;;;568        else
;;;569        {
;;;570          FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
000018  4a0e              LDR      r2,|L9.84|
00001a  6812              LDR      r2,[r2,#0]
00001c  f0420240          ORR      r2,r2,#0x40
000020  f04f4320          MOV      r3,#0xa0000000
000024  f8c32080          STR      r2,[r3,#0x80]
000028  e012              B        |L9.80|
                  |L9.42|
;;;571        }
;;;572      }
;;;573      else
;;;574      {
;;;575        /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
;;;576        if(FSMC_Bank == FSMC_Bank2_NAND)
00002a  2810              CMP      r0,#0x10
00002c  d108              BNE      |L9.64|
;;;577        {
;;;578          FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
00002e  f04f4220          MOV      r2,#0xa0000000
000032  6e12              LDR      r2,[r2,#0x60]
000034  4b08              LDR      r3,|L9.88|
000036  401a              ANDS     r2,r2,r3
000038  f04f4320          MOV      r3,#0xa0000000
00003c  661a              STR      r2,[r3,#0x60]
00003e  e007              B        |L9.80|
                  |L9.64|
;;;579        }
;;;580        else
;;;581        {
;;;582          FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
000040  4a04              LDR      r2,|L9.84|
000042  6812              LDR      r2,[r2,#0]
000044  4b04              LDR      r3,|L9.88|
000046  401a              ANDS     r2,r2,r3
000048  f04f4320          MOV      r3,#0xa0000000
00004c  f8c32080          STR      r2,[r3,#0x80]
                  |L9.80|
;;;583        }
;;;584      }
;;;585    }
000050  4770              BX       lr
;;;586    
                          ENDP

000052  0000              DCW      0x0000
                  |L9.84|
                          DCD      0xa0000080
                  |L9.88|
                          DCD      0x000fffbf

                          AREA ||i.FSMC_NANDInit||, CODE, READONLY, ALIGN=2

                  FSMC_NANDInit PROC
;;;255      */
;;;256    void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;257    {
;;;258      uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
000002  2100              MOVS     r1,#0
000004  2200              MOVS     r2,#0
000006  2300              MOVS     r3,#0
;;;259        
;;;260      /* Check the parameters */
;;;261      assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
;;;262      assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
;;;263      assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
;;;264      assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
;;;265      assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
;;;266      assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
;;;267      assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
;;;268      assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
;;;269      assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
;;;270      assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
;;;271      assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
;;;272      assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
;;;273      assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
;;;274      assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
;;;275      assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
;;;276      
;;;277      /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
;;;278      tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
000008  6844              LDR      r4,[r0,#4]
00000a  f0440408          ORR      r4,r4,#8
00000e  6885              LDR      r5,[r0,#8]
000010  432c              ORRS     r4,r4,r5
000012  68c5              LDR      r5,[r0,#0xc]
000014  432c              ORRS     r4,r4,r5
000016  6905              LDR      r5,[r0,#0x10]
000018  432c              ORRS     r4,r4,r5
00001a  6945              LDR      r5,[r0,#0x14]
00001c  ea442445          ORR      r4,r4,r5,LSL #9
000020  6985              LDR      r5,[r0,#0x18]
000022  ea443145          ORR      r1,r4,r5,LSL #13
;;;279                PCR_MemoryType_NAND |
;;;280                FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
;;;281                FSMC_NANDInitStruct->FSMC_ECC |
;;;282                FSMC_NANDInitStruct->FSMC_ECCPageSize |
;;;283                (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
;;;284                (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
;;;285                
;;;286      /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
;;;287      tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
000026  69c4              LDR      r4,[r0,#0x1c]
000028  6824              LDR      r4,[r4,#0]
00002a  69c5              LDR      r5,[r0,#0x1c]
00002c  686d              LDR      r5,[r5,#4]
00002e  ea442405          ORR      r4,r4,r5,LSL #8
000032  69c5              LDR      r5,[r0,#0x1c]
000034  68ad              LDR      r5,[r5,#8]
000036  ea444405          ORR      r4,r4,r5,LSL #16
00003a  69c5              LDR      r5,[r0,#0x1c]
00003c  68ed              LDR      r5,[r5,#0xc]
00003e  ea446205          ORR      r2,r4,r5,LSL #24
;;;288                (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;289                (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;290                (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
;;;291                
;;;292      /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
;;;293      tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
000042  6a04              LDR      r4,[r0,#0x20]
000044  6824              LDR      r4,[r4,#0]
000046  6a05              LDR      r5,[r0,#0x20]
000048  686d              LDR      r5,[r5,#4]
00004a  ea442405          ORR      r4,r4,r5,LSL #8
00004e  6a05              LDR      r5,[r0,#0x20]
000050  68ad              LDR      r5,[r5,#8]
000052  ea444405          ORR      r4,r4,r5,LSL #16
000056  6a05              LDR      r5,[r0,#0x20]
000058  68ed              LDR      r5,[r5,#0xc]
00005a  ea446305          ORR      r3,r4,r5,LSL #24
;;;294                (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;295                (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;296                (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;297      
;;;298      if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
00005e  6804              LDR      r4,[r0,#0]
000060  2c10              CMP      r4,#0x10
000062  d105              BNE      |L10.112|
;;;299      {
;;;300        /* FSMC_Bank2_NAND registers configuration */
;;;301        FSMC_Bank2->PCR2 = tmppcr;
000064  f04f4420          MOV      r4,#0xa0000000
000068  6621              STR      r1,[r4,#0x60]
;;;302        FSMC_Bank2->PMEM2 = tmppmem;
00006a  66a2              STR      r2,[r4,#0x68]
;;;303        FSMC_Bank2->PATT2 = tmppatt;
00006c  66e3              STR      r3,[r4,#0x6c]
00006e  e008              B        |L10.130|
                  |L10.112|
;;;304      }
;;;305      else
;;;306      {
;;;307        /* FSMC_Bank3_NAND registers configuration */
;;;308        FSMC_Bank3->PCR3 = tmppcr;
000070  4c04              LDR      r4,|L10.132|
000072  6021              STR      r1,[r4,#0]
;;;309        FSMC_Bank3->PMEM3 = tmppmem;
000074  f04f4420          MOV      r4,#0xa0000000
000078  f8c42088          STR      r2,[r4,#0x88]
;;;310        FSMC_Bank3->PATT3 = tmppatt;
00007c  4c01              LDR      r4,|L10.132|
00007e  340c              ADDS     r4,r4,#0xc
000080  6023              STR      r3,[r4,#0]
                  |L10.130|
;;;311      }
;;;312    }
000082  bd30              POP      {r4,r5,pc}
;;;313    
                          ENDP

                  |L10.132|
                          DCD      0xa0000080

                          AREA ||i.FSMC_NANDStructInit||, CODE, READONLY, ALIGN=1

                  FSMC_NANDStructInit PROC
;;;409      */
;;;410    void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
000000  2110              MOVS     r1,#0x10
;;;411    { 
;;;412      /* Reset NAND Init structure parameters values */
;;;413      FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
000002  6001              STR      r1,[r0,#0]
;;;414      FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
000004  2100              MOVS     r1,#0
000006  6041              STR      r1,[r0,#4]
;;;415      FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
000008  6081              STR      r1,[r0,#8]
;;;416      FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
00000a  60c1              STR      r1,[r0,#0xc]
;;;417      FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
00000c  6101              STR      r1,[r0,#0x10]
;;;418      FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
00000e  6141              STR      r1,[r0,#0x14]
;;;419      FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
000010  6181              STR      r1,[r0,#0x18]
;;;420      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000012  21fc              MOVS     r1,#0xfc
000014  69c2              LDR      r2,[r0,#0x1c]
000016  6011              STR      r1,[r2,#0]
;;;421      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
000018  69c2              LDR      r2,[r0,#0x1c]
00001a  6051              STR      r1,[r2,#4]
;;;422      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00001c  69c2              LDR      r2,[r0,#0x1c]
00001e  6091              STR      r1,[r2,#8]
;;;423      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000020  69c2              LDR      r2,[r0,#0x1c]
000022  60d1              STR      r1,[r2,#0xc]
;;;424      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000024  6a02              LDR      r2,[r0,#0x20]
000026  6011              STR      r1,[r2,#0]
;;;425      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
000028  6a02              LDR      r2,[r0,#0x20]
00002a  6051              STR      r1,[r2,#4]
;;;426      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00002c  6a02              LDR      r2,[r0,#0x20]
00002e  6091              STR      r1,[r2,#8]
;;;427      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	  
000030  6a02              LDR      r2,[r0,#0x20]
000032  60d1              STR      r1,[r2,#0xc]
;;;428    }
000034  4770              BX       lr
;;;429    
                          ENDP


                          AREA ||i.FSMC_NORSRAMCmd||, CODE, READONLY, ALIGN=2

                  FSMC_NORSRAMCmd PROC
;;;466      */
;;;467    void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
000000  b151              CBZ      r1,|L12.24|
;;;468    {
;;;469      assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
;;;470      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;471      
;;;472      if (NewState != DISABLE)
;;;473      {
;;;474        /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
;;;475        FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
000002  f04f4220          MOV      r2,#0xa0000000
000006  f8522020          LDR      r2,[r2,r0,LSL #2]
00000a  f0420201          ORR      r2,r2,#1
00000e  f04f4320          MOV      r3,#0xa0000000
000012  f8432020          STR      r2,[r3,r0,LSL #2]
000016  e009              B        |L12.44|
                  |L12.24|
;;;476      }
;;;477      else
;;;478      {
;;;479        /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
;;;480        FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
000018  f04f4220          MOV      r2,#0xa0000000
00001c  f8522020          LDR      r2,[r2,r0,LSL #2]
000020  4b03              LDR      r3,|L12.48|

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