stm32f10x_fsmc.txt
来自「STM32手持式示波器源代码」· 文本 代码 · 共 1,396 行 · 第 1/5 页
TXT
1,396 行
;;;797 itstatus = tmpsr & FSMC_IT;
00002a ea030401 AND r4,r3,r1
;;;798
;;;799 itenable = tmpsr & (FSMC_IT >> 3);
00002e ea0305d1 AND r5,r3,r1,LSR #3
;;;800 if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
000032 b114 CBZ r4,|L5.58|
000034 b10d CBZ r5,|L5.58|
;;;801 {
;;;802 bitstatus = SET;
000036 2001 MOVS r0,#1
000038 e000 B |L5.60|
|L5.58|
;;;803 }
;;;804 else
;;;805 {
;;;806 bitstatus = RESET;
00003a 2000 MOVS r0,#0
|L5.60|
;;;807 }
;;;808 return bitstatus;
;;;809 }
00003c bd70 POP {r4-r6,pc}
;;;810
ENDP
00003e 0000 DCW 0x0000
|L5.64|
DCD 0xa0000084
AREA ||i.FSMC_ITConfig||, CODE, READONLY, ALIGN=2
FSMC_ITConfig PROC
;;;628 */
;;;629 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
000000 b510 PUSH {r4,lr}
;;;630 {
;;;631 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
;;;632 assert_param(IS_FSMC_IT(FSMC_IT));
;;;633 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;634
;;;635 if (NewState != DISABLE)
000002 b1ea CBZ r2,|L6.64|
;;;636 {
;;;637 /* Enable the selected FSMC_Bank2 interrupts */
;;;638 if(FSMC_Bank == FSMC_Bank2_NAND)
000004 2810 CMP r0,#0x10
000006 d107 BNE |L6.24|
;;;639 {
;;;640 FSMC_Bank2->SR2 |= FSMC_IT;
000008 f04f4320 MOV r3,#0xa0000000
00000c 6e5b LDR r3,[r3,#0x64]
00000e 430b ORRS r3,r3,r1
000010 f04f4420 MOV r4,#0xa0000000
000014 6663 STR r3,[r4,#0x64]
000016 e030 B |L6.122|
|L6.24|
;;;641 }
;;;642 /* Enable the selected FSMC_Bank3 interrupts */
;;;643 else if (FSMC_Bank == FSMC_Bank3_NAND)
000018 f5b07f80 CMP r0,#0x100
00001c d107 BNE |L6.46|
;;;644 {
;;;645 FSMC_Bank3->SR3 |= FSMC_IT;
00001e 4b17 LDR r3,|L6.124|
000020 681b LDR r3,[r3,#0]
000022 430b ORRS r3,r3,r1
000024 f04f4420 MOV r4,#0xa0000000
000028 f8c43084 STR r3,[r4,#0x84]
00002c e025 B |L6.122|
|L6.46|
;;;646 }
;;;647 /* Enable the selected FSMC_Bank4 interrupts */
;;;648 else
;;;649 {
;;;650 FSMC_Bank4->SR4 |= FSMC_IT;
00002e 4b13 LDR r3,|L6.124|
000030 3320 ADDS r3,r3,#0x20
000032 681b LDR r3,[r3,#0]
000034 430b ORRS r3,r3,r1
000036 f04f4420 MOV r4,#0xa0000000
00003a f8c430a4 STR r3,[r4,#0xa4]
00003e e01c B |L6.122|
|L6.64|
;;;651 }
;;;652 }
;;;653 else
;;;654 {
;;;655 /* Disable the selected FSMC_Bank2 interrupts */
;;;656 if(FSMC_Bank == FSMC_Bank2_NAND)
000040 2810 CMP r0,#0x10
000042 d107 BNE |L6.84|
;;;657 {
;;;658
;;;659 FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
000044 f04f4320 MOV r3,#0xa0000000
000048 6e5b LDR r3,[r3,#0x64]
00004a 438b BICS r3,r3,r1
00004c f04f4420 MOV r4,#0xa0000000
000050 6663 STR r3,[r4,#0x64]
000052 e012 B |L6.122|
|L6.84|
;;;660 }
;;;661 /* Disable the selected FSMC_Bank3 interrupts */
;;;662 else if (FSMC_Bank == FSMC_Bank3_NAND)
000054 f5b07f80 CMP r0,#0x100
000058 d107 BNE |L6.106|
;;;663 {
;;;664 FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
00005a 4b08 LDR r3,|L6.124|
00005c 681b LDR r3,[r3,#0]
00005e 438b BICS r3,r3,r1
000060 f04f4420 MOV r4,#0xa0000000
000064 f8c43084 STR r3,[r4,#0x84]
000068 e007 B |L6.122|
|L6.106|
;;;665 }
;;;666 /* Disable the selected FSMC_Bank4 interrupts */
;;;667 else
;;;668 {
;;;669 FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
00006a 4b04 LDR r3,|L6.124|
00006c 3320 ADDS r3,r3,#0x20
00006e 681b LDR r3,[r3,#0]
000070 438b BICS r3,r3,r1
000072 f04f4420 MOV r4,#0xa0000000
000076 f8c430a4 STR r3,[r4,#0xa4]
|L6.122|
;;;670 }
;;;671 }
;;;672 }
00007a bd10 POP {r4,pc}
;;;673
ENDP
|L6.124|
DCD 0xa0000084
AREA ||i.FSMC_NANDCmd||, CODE, READONLY, ALIGN=2
FSMC_NANDCmd PROC
;;;492 */
;;;493 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
000000 b199 CBZ r1,|L7.42|
;;;494 {
;;;495 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;496 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;497
;;;498 if (NewState != DISABLE)
;;;499 {
;;;500 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
;;;501 if(FSMC_Bank == FSMC_Bank2_NAND)
000002 2810 CMP r0,#0x10
000004 d108 BNE |L7.24|
;;;502 {
;;;503 FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
000006 f04f4220 MOV r2,#0xa0000000
00000a 6e12 LDR r2,[r2,#0x60]
00000c f0420204 ORR r2,r2,#4
000010 f04f4320 MOV r3,#0xa0000000
000014 661a STR r2,[r3,#0x60]
000016 e01b B |L7.80|
|L7.24|
;;;504 }
;;;505 else
;;;506 {
;;;507 FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
000018 4a0e LDR r2,|L7.84|
00001a 6812 LDR r2,[r2,#0]
00001c f0420204 ORR r2,r2,#4
000020 f04f4320 MOV r3,#0xa0000000
000024 f8c32080 STR r2,[r3,#0x80]
000028 e012 B |L7.80|
|L7.42|
;;;508 }
;;;509 }
;;;510 else
;;;511 {
;;;512 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
;;;513 if(FSMC_Bank == FSMC_Bank2_NAND)
00002a 2810 CMP r0,#0x10
00002c d108 BNE |L7.64|
;;;514 {
;;;515 FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
00002e f04f4220 MOV r2,#0xa0000000
000032 6e12 LDR r2,[r2,#0x60]
000034 4b08 LDR r3,|L7.88|
000036 401a ANDS r2,r2,r3
000038 f04f4320 MOV r3,#0xa0000000
00003c 661a STR r2,[r3,#0x60]
00003e e007 B |L7.80|
|L7.64|
;;;516 }
;;;517 else
;;;518 {
;;;519 FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
000040 4a04 LDR r2,|L7.84|
000042 6812 LDR r2,[r2,#0]
000044 4b04 LDR r3,|L7.88|
000046 401a ANDS r2,r2,r3
000048 f04f4320 MOV r3,#0xa0000000
00004c f8c32080 STR r2,[r3,#0x80]
|L7.80|
;;;520 }
;;;521 }
;;;522 }
000050 4770 BX lr
;;;523
ENDP
000052 0000 DCW 0x0000
|L7.84|
DCD 0xa0000080
|L7.88|
DCD 0x000ffffb
AREA ||i.FSMC_NANDDeInit||, CODE, READONLY, ALIGN=2
FSMC_NANDDeInit PROC
;;;127 */
;;;128 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
000000 2810 CMP r0,#0x10
;;;129 {
;;;130 /* Check the parameter */
;;;131 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;132
;;;133 if(FSMC_Bank == FSMC_Bank2_NAND)
000002 d10a BNE |L8.26|
;;;134 {
;;;135 /* Set the FSMC_Bank2 registers to their reset values */
;;;136 FSMC_Bank2->PCR2 = 0x00000018;
000004 2118 MOVS r1,#0x18
000006 f04f4220 MOV r2,#0xa0000000
00000a 6611 STR r1,[r2,#0x60]
;;;137 FSMC_Bank2->SR2 = 0x00000040;
00000c 2140 MOVS r1,#0x40
00000e 6651 STR r1,[r2,#0x64]
;;;138 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
000010 f04f31fc MOV r1,#0xfcfcfcfc
000014 6691 STR r1,[r2,#0x68]
;;;139 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
000016 66d1 STR r1,[r2,#0x6c]
000018 e010 B |L8.60|
|L8.26|
;;;140 }
;;;141 /* FSMC_Bank3_NAND */
;;;142 else
;;;143 {
;;;144 /* Set the FSMC_Bank3 registers to their reset values */
;;;145 FSMC_Bank3->PCR3 = 0x00000018;
00001a 2118 MOVS r1,#0x18
00001c 4a08 LDR r2,|L8.64|
00001e 6011 STR r1,[r2,#0]
;;;146 FSMC_Bank3->SR3 = 0x00000040;
000020 2140 MOVS r1,#0x40
000022 f04f4220 MOV r2,#0xa0000000
000026 f8c21084 STR r1,[r2,#0x84]
;;;147 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
00002a f04f31fc MOV r1,#0xfcfcfcfc
00002e 4a04 LDR r2,|L8.64|
000030 3208 ADDS r2,r2,#8
000032 6011 STR r1,[r2,#0]
;;;148 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
000034 f04f4220 MOV r2,#0xa0000000
000038 f8c2108c STR r1,[r2,#0x8c]
|L8.60|
;;;149 }
;;;150 }
00003c 4770 BX lr
;;;151
ENDP
00003e 0000 DCW 0x0000
|L8.64|
DCD 0xa0000080
AREA ||i.FSMC_NANDECCCmd||, CODE, READONLY, ALIGN=2
FSMC_NANDECCCmd PROC
;;;555 */
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