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📄 stm32f10x_dma.txt

📁 STM32手持式示波器源代码
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000134  3150              ADDS     r1,r1,#0x50
000136  4288              CMP      r0,r1
000138  d108              BNE      |L4.332|
;;;186        {
;;;187          /* Reset interrupt pending bits for DMA2 Channel5 */
;;;188          DMA2->IFCR |= DMA2_Channel5_IT_Mask;
00013a  4906              LDR      r1,|L4.340|
00013c  1f09              SUBS     r1,r1,#4
00013e  6809              LDR      r1,[r1,#0]
000140  f4412170          ORR      r1,r1,#0xf0000
000144  4a02              LDR      r2,|L4.336|
000146  3a08              SUBS     r2,r2,#8
000148  f8c21404          STR      r1,[r2,#0x404]
                  |L4.332|
;;;189        }
;;;190      }
;;;191    }
00014c  4770              BX       lr
;;;192    
                          ENDP

00014e  0000              DCW      0x0000
                  |L4.336|
                          DCD      0x40020008
                  |L4.340|
                          DCD      0x40020408

                          AREA ||i.DMA_GetCurrDataCounter||, CODE, READONLY, ALIGN=1

                  DMA_GetCurrDataCounter PROC
;;;351      */
;;;352    uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
000000  4601              MOV      r1,r0
;;;353    {
;;;354      /* Check the parameters */
;;;355      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;356      /* Return the number of remaining data units for DMAy Channelx */
;;;357      return ((uint16_t)(DMAy_Channelx->CNDTR));
000002  6848              LDR      r0,[r1,#4]
000004  b280              UXTH     r0,r0
;;;358    }
000006  4770              BX       lr
;;;359    
                          ENDP


                          AREA ||i.DMA_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  DMA_GetFlagStatus PROC
;;;413      */
;;;414    FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
000000  4602              MOV      r2,r0
;;;415    {
;;;416      FlagStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;417      uint32_t tmpreg = 0;
000004  2100              MOVS     r1,#0
;;;418      /* Check the parameters */
;;;419      assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
;;;420    
;;;421      /* Calculate the used DMA */
;;;422      if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
000006  f0125f80          TST      r2,#0x10000000
00000a  d002              BEQ      |L6.18|
;;;423      {
;;;424        /* Get DMA2 ISR register value */
;;;425        tmpreg = DMA2->ISR ;
00000c  4b05              LDR      r3,|L6.36|
00000e  6819              LDR      r1,[r3,#0]
000010  e001              B        |L6.22|
                  |L6.18|
;;;426      }
;;;427      else
;;;428      {
;;;429        /* Get DMA1 ISR register value */
;;;430        tmpreg = DMA1->ISR ;
000012  4b05              LDR      r3,|L6.40|
000014  6819              LDR      r1,[r3,#0]
                  |L6.22|
;;;431      }
;;;432    
;;;433      /* Check the status of the specified DMA flag */
;;;434      if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
000016  4211              TST      r1,r2
000018  d001              BEQ      |L6.30|
;;;435      {
;;;436        /* DMA_FLAG is set */
;;;437        bitstatus = SET;
00001a  2001              MOVS     r0,#1
00001c  e000              B        |L6.32|
                  |L6.30|
;;;438      }
;;;439      else
;;;440      {
;;;441        /* DMA_FLAG is reset */
;;;442        bitstatus = RESET;
00001e  2000              MOVS     r0,#0
                  |L6.32|
;;;443      }
;;;444      
;;;445      /* Return the DMA_FLAG status */
;;;446      return  bitstatus;
;;;447    }
000020  4770              BX       lr
;;;448    
                          ENDP

000022  0000              DCW      0x0000
                  |L6.36|
                          DCD      0x40020400
                  |L6.40|
                          DCD      0x40020000

                          AREA ||i.DMA_GetITStatus||, CODE, READONLY, ALIGN=2

                  DMA_GetITStatus PROC
;;;574      */
;;;575    ITStatus DMA_GetITStatus(uint32_t DMA_IT)
000000  4602              MOV      r2,r0
;;;576    {
;;;577      ITStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;578      uint32_t tmpreg = 0;
000004  2100              MOVS     r1,#0
;;;579      /* Check the parameters */
;;;580      assert_param(IS_DMA_GET_IT(DMA_IT));
;;;581    
;;;582      /* Calculate the used DMA */
;;;583      if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
000006  f0125f80          TST      r2,#0x10000000
00000a  d002              BEQ      |L7.18|
;;;584      {
;;;585        /* Get DMA2 ISR register value */
;;;586        tmpreg = DMA2->ISR ;
00000c  4b05              LDR      r3,|L7.36|
00000e  6819              LDR      r1,[r3,#0]
000010  e001              B        |L7.22|
                  |L7.18|
;;;587      }
;;;588      else
;;;589      {
;;;590        /* Get DMA1 ISR register value */
;;;591        tmpreg = DMA1->ISR ;
000012  4b05              LDR      r3,|L7.40|
000014  6819              LDR      r1,[r3,#0]
                  |L7.22|
;;;592      }
;;;593    
;;;594      /* Check the status of the specified DMA interrupt */
;;;595      if ((tmpreg & DMA_IT) != (uint32_t)RESET)
000016  4211              TST      r1,r2
000018  d001              BEQ      |L7.30|
;;;596      {
;;;597        /* DMA_IT is set */
;;;598        bitstatus = SET;
00001a  2001              MOVS     r0,#1
00001c  e000              B        |L7.32|
                  |L7.30|
;;;599      }
;;;600      else
;;;601      {
;;;602        /* DMA_IT is reset */
;;;603        bitstatus = RESET;
00001e  2000              MOVS     r0,#0
                  |L7.32|
;;;604      }
;;;605      /* Return the DMA_IT status */
;;;606      return  bitstatus;
;;;607    }
000020  4770              BX       lr
;;;608    
                          ENDP

000022  0000              DCW      0x0000
                  |L7.36|
                          DCD      0x40020400
                  |L7.40|
                          DCD      0x40020000

                          AREA ||i.DMA_ITConfig||, CODE, READONLY, ALIGN=1

                  DMA_ITConfig PROC
;;;325      */
;;;326    void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
000000  b11a              CBZ      r2,|L8.10|
;;;327    {
;;;328      /* Check the parameters */
;;;329      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;330      assert_param(IS_DMA_CONFIG_IT(DMA_IT));
;;;331      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;332      if (NewState != DISABLE)
;;;333      {
;;;334        /* Enable the selected DMA interrupts */
;;;335        DMAy_Channelx->CCR |= DMA_IT;
000002  6803              LDR      r3,[r0,#0]
000004  430b              ORRS     r3,r3,r1
000006  6003              STR      r3,[r0,#0]
000008  e002              B        |L8.16|
                  |L8.10|
;;;336      }
;;;337      else
;;;338      {
;;;339        /* Disable the selected DMA interrupts */
;;;340        DMAy_Channelx->CCR &= ~DMA_IT;
00000a  6803              LDR      r3,[r0,#0]
00000c  438b              BICS     r3,r3,r1
00000e  6003              STR      r3,[r0,#0]
                  |L8.16|
;;;341      }
;;;342    }
000010  4770              BX       lr
;;;343    
                          ENDP


                          AREA ||i.DMA_Init||, CODE, READONLY, ALIGN=1

                  DMA_Init PROC
;;;201      */
;;;202    void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
000000  b510              PUSH     {r4,lr}
;;;203    {
;;;204      uint32_t tmpreg = 0;
000002  2200              MOVS     r2,#0
;;;205    
;;;206      /* Check the parameters */
;;;207      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;208      assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
;;;209      assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
;;;210      assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
;;;211      assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));   
;;;212      assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
;;;213      assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
;;;214      assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
;;;215      assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
;;;216      assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
;;;217    
;;;218    /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
;;;219      /* Get the DMAy_Channelx CCR value */
;;;220      tmpreg = DMAy_Channelx->CCR;
000004  6802              LDR      r2,[r0,#0]
;;;221      /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
;;;222      tmpreg &= CCR_CLEAR_Mask;
000006  f64773f0          MOV      r3,#0x7ff0
00000a  439a              BICS     r2,r2,r3
;;;223      /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
;;;224      /* Set DIR bit according to DMA_DIR value */
;;;225      /* Set CIRC bit according to DMA_Mode value */
;;;226      /* Set PINC bit according to DMA_PeripheralInc value */
;;;227      /* Set MINC bit according to DMA_MemoryInc value */
;;;228      /* Set PSIZE bits according to DMA_PeripheralDataSize value */
;;;229      /* Set MSIZE bits according to DMA_MemoryDataSize value */
;;;230      /* Set PL bits according to DMA_Priority value */
;;;231      /* Set the MEM2MEM bit according to DMA_M2M value */
;;;232      tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
00000c  6a0c              LDR      r4,[r1,#0x20]
00000e  688b              LDR      r3,[r1,#8]
000010  4323              ORRS     r3,r3,r4
000012  690c              LDR      r4,[r1,#0x10]
000014  4323              ORRS     r3,r3,r4
000016  694c              LDR      r4,[r1,#0x14]
000018  4323              ORRS     r3,r3,r4
00001a  698c              LDR      r4,[r1,#0x18]
00001c  4323              ORRS     r3,r3,r4
00001e  69cc              LDR      r4,[r1,#0x1c]
000020  4323              ORRS     r3,r3,r4
000022  6a4c              LDR      r4,[r1,#0x24]
000024  4323              ORRS     r3,r3,r4
000026  6a8c              LDR      r4,[r1,#0x28]
000028  4323              ORRS     r3,r3,r4
00002a  431a              ORRS     r2,r2,r3
;;;233                DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
;;;234                DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
;;;235                DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
;;;236    
;;;237      /* Write to DMAy Channelx CCR */
;;;238      DMAy_Channelx->CCR = tmpreg;
00002c  6002              STR      r2,[r0,#0]
;;;239    
;;;240    /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
;;;241      /* Write to DMAy Channelx CNDTR */
;;;242      DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
00002e  68cb              LDR      r3,[r1,#0xc]
000030  6043              STR      r3,[r0,#4]
;;;243    
;;;244    /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
;;;245      /* Write to DMAy Channelx CPAR */
;;;246      DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
000032  680b              LDR      r3,[r1,#0]
000034  6083              STR      r3,[r0,#8]
;;;247    
;;;248    /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
;;;249      /* Write to DMAy Channelx CMAR */
;;;250      DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
000036  684b              LDR      r3,[r1,#4]
000038  60c3              STR      r3,[r0,#0xc]
;;;251    }
00003a  bd10              POP      {r4,pc}
;;;252    
                          ENDP


                          AREA ||i.DMA_StructInit||, CODE, READONLY, ALIGN=1

                  DMA_StructInit PROC
;;;258      */
;;;259    void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
000000  2100              MOVS     r1,#0
;;;260    {
;;;261    /*-------------- Reset DMA init structure parameters values ------------------*/
;;;262      /* Initialize the DMA_PeripheralBaseAddr member */
;;;263      DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
000002  6001              STR      r1,[r0,#0]
;;;264      /* Initialize the DMA_MemoryBaseAddr member */
;;;265      DMA_InitStruct->DMA_MemoryBaseAddr = 0;
000004  6041              STR      r1,[r0,#4]
;;;266      /* Initialize the DMA_DIR member */
;;;267      DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
000006  6081              STR      r1,[r0,#8]
;;;268      /* Initialize the DMA_BufferSize member */
;;;269      DMA_InitStruct->DMA_BufferSize = 0;
000008  60c1              STR      r1,[r0,#0xc]
;;;270      /* Initialize the DMA_PeripheralInc member */
;;;271      DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00000a  6101              STR      r1,[r0,#0x10]
;;;272      /* Initialize the DMA_MemoryInc member */
;;;273      DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00000c  6141              STR      r1,[r0,#0x14]
;;;274      /* Initialize the DMA_PeripheralDataSize member */
;;;275      DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00000e  6181              STR      r1,[r0,#0x18]
;;;276      /* Initialize the DMA_MemoryDataSize member */
;;;277      DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
000010  61c1              STR      r1,[r0,#0x1c]
;;;278      /* Initialize the DMA_Mode member */
;;;279      DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
000012  6201              STR      r1,[r0,#0x20]
;;;280      /* Initialize the DMA_Priority member */
;;;281      DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
000014  6241              STR      r1,[r0,#0x24]
;;;282      /* Initialize the DMA_M2M member */
;;;283      DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
000016  6281              STR      r1,[r0,#0x28]
;;;284    }
000018  4770              BX       lr
;;;285    
                          ENDP

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