📄 stm32f10x_dma.txt
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; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_dma.o --depend=.\Obj\stm32f10x_dma.d --device=DARMSTM --apcs=interwork -O0 -Otime -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Source\inc -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c]
THUMB
AREA ||i.DMA_ClearFlag||, CODE, READONLY, ALIGN=2
DMA_ClearFlag PROC
;;;502 */
;;;503 void DMA_ClearFlag(uint32_t DMA_FLAG)
000000 f0105f80 TST r0,#0x10000000
;;;504 {
;;;505 /* Check the parameters */
;;;506 assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
;;;507 /* Calculate the used DMA */
;;;508
;;;509 if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
000004 d002 BEQ |L1.12|
;;;510 {
;;;511 /* Clear the selected DMA flags */
;;;512 DMA2->IFCR = DMA_FLAG;
000006 4903 LDR r1,|L1.20|
000008 6008 STR r0,[r1,#0]
00000a e001 B |L1.16|
|L1.12|
;;;513 }
;;;514 else
;;;515 {
;;;516 /* Clear the selected DMA flags */
;;;517 DMA1->IFCR = DMA_FLAG;
00000c 4902 LDR r1,|L1.24|
00000e 6048 STR r0,[r1,#4]
|L1.16|
;;;518 }
;;;519 }
000010 4770 BX lr
;;;520
ENDP
000012 0000 DCW 0x0000
|L1.20|
DCD 0x40020404
|L1.24|
DCD 0x40020000
AREA ||i.DMA_ClearITPendingBit||, CODE, READONLY, ALIGN=2
DMA_ClearITPendingBit PROC
;;;662 */
;;;663 void DMA_ClearITPendingBit(uint32_t DMA_IT)
000000 f0105f80 TST r0,#0x10000000
;;;664 {
;;;665 /* Check the parameters */
;;;666 assert_param(IS_DMA_CLEAR_IT(DMA_IT));
;;;667
;;;668 /* Calculate the used DMA */
;;;669 if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
000004 d002 BEQ |L2.12|
;;;670 {
;;;671 /* Clear the selected DMA interrupt pending bits */
;;;672 DMA2->IFCR = DMA_IT;
000006 4903 LDR r1,|L2.20|
000008 6008 STR r0,[r1,#0]
00000a e001 B |L2.16|
|L2.12|
;;;673 }
;;;674 else
;;;675 {
;;;676 /* Clear the selected DMA interrupt pending bits */
;;;677 DMA1->IFCR = DMA_IT;
00000c 4902 LDR r1,|L2.24|
00000e 6048 STR r0,[r1,#4]
|L2.16|
;;;678 }
;;;679 }
000010 4770 BX lr
;;;680
ENDP
000012 0000 DCW 0x0000
|L2.20|
DCD 0x40020404
|L2.24|
DCD 0x40020000
AREA ||i.DMA_Cmd||, CODE, READONLY, ALIGN=1
DMA_Cmd PROC
;;;293 */
;;;294 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
000000 b121 CBZ r1,|L3.12|
;;;295 {
;;;296 /* Check the parameters */
;;;297 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;298 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;299
;;;300 if (NewState != DISABLE)
;;;301 {
;;;302 /* Enable the selected DMAy Channelx */
;;;303 DMAy_Channelx->CCR |= CCR_ENABLE_Set;
000002 6802 LDR r2,[r0,#0]
000004 f0420201 ORR r2,r2,#1
000008 6002 STR r2,[r0,#0]
00000a e003 B |L3.20|
|L3.12|
;;;304 }
;;;305 else
;;;306 {
;;;307 /* Disable the selected DMAy Channelx */
;;;308 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
00000c 6802 LDR r2,[r0,#0]
00000e f0220201 BIC r2,r2,#1
000012 6002 STR r2,[r0,#0]
|L3.20|
;;;309 }
;;;310 }
000014 4770 BX lr
;;;311
ENDP
AREA ||i.DMA_DeInit||, CODE, READONLY, ALIGN=2
DMA_DeInit PROC
;;;109 */
;;;110 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
000000 6801 LDR r1,[r0,#0]
;;;111 {
;;;112 /* Check the parameters */
;;;113 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;114 /* Disable the selected DMAy Channelx */
;;;115 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
000002 f0210101 BIC r1,r1,#1
000006 6001 STR r1,[r0,#0]
;;;116 /* Reset DMAy Channelx control register */
;;;117 DMAy_Channelx->CCR = 0;
000008 2100 MOVS r1,#0
00000a 6001 STR r1,[r0,#0]
;;;118
;;;119 /* Reset DMAy Channelx remaining bytes register */
;;;120 DMAy_Channelx->CNDTR = 0;
00000c 6041 STR r1,[r0,#4]
;;;121
;;;122 /* Reset DMAy Channelx peripheral address register */
;;;123 DMAy_Channelx->CPAR = 0;
00000e 6081 STR r1,[r0,#8]
;;;124
;;;125 /* Reset DMAy Channelx memory address register */
;;;126 DMAy_Channelx->CMAR = 0;
000010 60c1 STR r1,[r0,#0xc]
;;;127
;;;128 if (DMAy_Channelx == DMA1_Channel1)
000012 494f LDR r1,|L4.336|
000014 4288 CMP r0,r1
000016 d108 BNE |L4.42|
;;;129 {
;;;130 /* Reset interrupt pending bits for DMA1 Channel1 */
;;;131 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
000018 494d LDR r1,|L4.336|
00001a 3908 SUBS r1,r1,#8
00001c 6849 LDR r1,[r1,#4]
00001e f041010f ORR r1,r1,#0xf
000022 4a4b LDR r2,|L4.336|
000024 3a08 SUBS r2,r2,#8
000026 6051 STR r1,[r2,#4]
000028 e090 B |L4.332|
|L4.42|
;;;132 }
;;;133 else if (DMAy_Channelx == DMA1_Channel2)
00002a 4949 LDR r1,|L4.336|
00002c 3114 ADDS r1,r1,#0x14
00002e 4288 CMP r0,r1
000030 d108 BNE |L4.68|
;;;134 {
;;;135 /* Reset interrupt pending bits for DMA1 Channel2 */
;;;136 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
000032 4947 LDR r1,|L4.336|
000034 3908 SUBS r1,r1,#8
000036 6849 LDR r1,[r1,#4]
000038 f04101f0 ORR r1,r1,#0xf0
00003c 4a44 LDR r2,|L4.336|
00003e 3a08 SUBS r2,r2,#8
000040 6051 STR r1,[r2,#4]
000042 e083 B |L4.332|
|L4.68|
;;;137 }
;;;138 else if (DMAy_Channelx == DMA1_Channel3)
000044 4942 LDR r1,|L4.336|
000046 3128 ADDS r1,r1,#0x28
000048 4288 CMP r0,r1
00004a d108 BNE |L4.94|
;;;139 {
;;;140 /* Reset interrupt pending bits for DMA1 Channel3 */
;;;141 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
00004c 4940 LDR r1,|L4.336|
00004e 3908 SUBS r1,r1,#8
000050 6849 LDR r1,[r1,#4]
000052 f4416170 ORR r1,r1,#0xf00
000056 4a3e LDR r2,|L4.336|
000058 3a08 SUBS r2,r2,#8
00005a 6051 STR r1,[r2,#4]
00005c e076 B |L4.332|
|L4.94|
;;;142 }
;;;143 else if (DMAy_Channelx == DMA1_Channel4)
00005e 493c LDR r1,|L4.336|
000060 313c ADDS r1,r1,#0x3c
000062 4288 CMP r0,r1
000064 d108 BNE |L4.120|
;;;144 {
;;;145 /* Reset interrupt pending bits for DMA1 Channel4 */
;;;146 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
000066 493a LDR r1,|L4.336|
000068 3908 SUBS r1,r1,#8
00006a 6849 LDR r1,[r1,#4]
00006c f4414170 ORR r1,r1,#0xf000
000070 4a37 LDR r2,|L4.336|
000072 3a08 SUBS r2,r2,#8
000074 6051 STR r1,[r2,#4]
000076 e069 B |L4.332|
|L4.120|
;;;147 }
;;;148 else if (DMAy_Channelx == DMA1_Channel5)
000078 4935 LDR r1,|L4.336|
00007a 3150 ADDS r1,r1,#0x50
00007c 4288 CMP r0,r1
00007e d108 BNE |L4.146|
;;;149 {
;;;150 /* Reset interrupt pending bits for DMA1 Channel5 */
;;;151 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
000080 4933 LDR r1,|L4.336|
000082 3908 SUBS r1,r1,#8
000084 6849 LDR r1,[r1,#4]
000086 f4412170 ORR r1,r1,#0xf0000
00008a 4a31 LDR r2,|L4.336|
00008c 3a08 SUBS r2,r2,#8
00008e 6051 STR r1,[r2,#4]
000090 e05c B |L4.332|
|L4.146|
;;;152 }
;;;153 else if (DMAy_Channelx == DMA1_Channel6)
000092 492f LDR r1,|L4.336|
000094 3164 ADDS r1,r1,#0x64
000096 4288 CMP r0,r1
000098 d108 BNE |L4.172|
;;;154 {
;;;155 /* Reset interrupt pending bits for DMA1 Channel6 */
;;;156 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
00009a 492d LDR r1,|L4.336|
00009c 3908 SUBS r1,r1,#8
00009e 6849 LDR r1,[r1,#4]
0000a0 f4410170 ORR r1,r1,#0xf00000
0000a4 4a2a LDR r2,|L4.336|
0000a6 3a08 SUBS r2,r2,#8
0000a8 6051 STR r1,[r2,#4]
0000aa e04f B |L4.332|
|L4.172|
;;;157 }
;;;158 else if (DMAy_Channelx == DMA1_Channel7)
0000ac 4928 LDR r1,|L4.336|
0000ae 3178 ADDS r1,r1,#0x78
0000b0 4288 CMP r0,r1
0000b2 d108 BNE |L4.198|
;;;159 {
;;;160 /* Reset interrupt pending bits for DMA1 Channel7 */
;;;161 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
0000b4 4926 LDR r1,|L4.336|
0000b6 3908 SUBS r1,r1,#8
0000b8 6849 LDR r1,[r1,#4]
0000ba f0416170 ORR r1,r1,#0xf000000
0000be 4a24 LDR r2,|L4.336|
0000c0 3a08 SUBS r2,r2,#8
0000c2 6051 STR r1,[r2,#4]
0000c4 e042 B |L4.332|
|L4.198|
;;;162 }
;;;163 else if (DMAy_Channelx == DMA2_Channel1)
0000c6 4923 LDR r1,|L4.340|
0000c8 4288 CMP r0,r1
0000ca d108 BNE |L4.222|
;;;164 {
;;;165 /* Reset interrupt pending bits for DMA2 Channel1 */
;;;166 DMA2->IFCR |= DMA2_Channel1_IT_Mask;
0000cc 1f01 SUBS r1,r0,#4
0000ce 6809 LDR r1,[r1,#0]
0000d0 f041010f ORR r1,r1,#0xf
0000d4 4a1e LDR r2,|L4.336|
0000d6 3a08 SUBS r2,r2,#8
0000d8 f8c21404 STR r1,[r2,#0x404]
0000dc e036 B |L4.332|
|L4.222|
;;;167 }
;;;168 else if (DMAy_Channelx == DMA2_Channel2)
0000de 491d LDR r1,|L4.340|
0000e0 3114 ADDS r1,r1,#0x14
0000e2 4288 CMP r0,r1
0000e4 d109 BNE |L4.250|
;;;169 {
;;;170 /* Reset interrupt pending bits for DMA2 Channel2 */
;;;171 DMA2->IFCR |= DMA2_Channel2_IT_Mask;
0000e6 491b LDR r1,|L4.340|
0000e8 1f09 SUBS r1,r1,#4
0000ea 6809 LDR r1,[r1,#0]
0000ec f04101f0 ORR r1,r1,#0xf0
0000f0 4a17 LDR r2,|L4.336|
0000f2 3a08 SUBS r2,r2,#8
0000f4 f8c21404 STR r1,[r2,#0x404]
0000f8 e028 B |L4.332|
|L4.250|
;;;172 }
;;;173 else if (DMAy_Channelx == DMA2_Channel3)
0000fa 4916 LDR r1,|L4.340|
0000fc 3128 ADDS r1,r1,#0x28
0000fe 4288 CMP r0,r1
000100 d109 BNE |L4.278|
;;;174 {
;;;175 /* Reset interrupt pending bits for DMA2 Channel3 */
;;;176 DMA2->IFCR |= DMA2_Channel3_IT_Mask;
000102 4914 LDR r1,|L4.340|
000104 1f09 SUBS r1,r1,#4
000106 6809 LDR r1,[r1,#0]
000108 f4416170 ORR r1,r1,#0xf00
00010c 4a10 LDR r2,|L4.336|
00010e 3a08 SUBS r2,r2,#8
000110 f8c21404 STR r1,[r2,#0x404]
000114 e01a B |L4.332|
|L4.278|
;;;177 }
;;;178 else if (DMAy_Channelx == DMA2_Channel4)
000116 490f LDR r1,|L4.340|
000118 313c ADDS r1,r1,#0x3c
00011a 4288 CMP r0,r1
00011c d109 BNE |L4.306|
;;;179 {
;;;180 /* Reset interrupt pending bits for DMA2 Channel4 */
;;;181 DMA2->IFCR |= DMA2_Channel4_IT_Mask;
00011e 490d LDR r1,|L4.340|
000120 1f09 SUBS r1,r1,#4
000122 6809 LDR r1,[r1,#0]
000124 f4414170 ORR r1,r1,#0xf000
000128 4a09 LDR r2,|L4.336|
00012a 3a08 SUBS r2,r2,#8
00012c f8c21404 STR r1,[r2,#0x404]
000130 e00c B |L4.332|
|L4.306|
;;;182 }
;;;183 else
;;;184 {
;;;185 if (DMAy_Channelx == DMA2_Channel5)
000132 4908 LDR r1,|L4.340|
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