📄 stm32f10x_rcc.txt
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;;;1227 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
000000 4901 LDR r1,|L11.8|
;;;1228 {
;;;1229 /* Check the parameters */
;;;1230 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1231 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
000002 64c8 STR r0,[r1,#0x4c]
;;;1232 }
000004 4770 BX lr
;;;1233
ENDP
000006 0000 DCW 0x0000
|L11.8|
DCD 0x42420000
AREA ||i.RCC_DeInit||, CODE, READONLY, ALIGN=2
RCC_DeInit PROC
;;;223 */
;;;224 void RCC_DeInit(void)
000000 480f LDR r0,|L12.64|
;;;225 {
;;;226 /* Set HSION bit */
;;;227 RCC->CR |= (uint32_t)0x00000001;
000002 6800 LDR r0,[r0,#0]
000004 f0400001 ORR r0,r0,#1
000008 490d LDR r1,|L12.64|
00000a 6008 STR r0,[r1,#0]
;;;228
;;;229 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
;;;230 #ifndef STM32F10X_CL
;;;231 RCC->CFGR &= (uint32_t)0xF8FF0000;
00000c 4608 MOV r0,r1
00000e 6840 LDR r0,[r0,#4]
000010 490c LDR r1,|L12.68|
000012 4008 ANDS r0,r0,r1
000014 490a LDR r1,|L12.64|
000016 6048 STR r0,[r1,#4]
;;;232 #else
;;;233 RCC->CFGR &= (uint32_t)0xF0FF0000;
;;;234 #endif /* STM32F10X_CL */
;;;235
;;;236 /* Reset HSEON, CSSON and PLLON bits */
;;;237 RCC->CR &= (uint32_t)0xFEF6FFFF;
000018 4608 MOV r0,r1
00001a 6800 LDR r0,[r0,#0]
00001c 490a LDR r1,|L12.72|
00001e 4008 ANDS r0,r0,r1
000020 4907 LDR r1,|L12.64|
000022 6008 STR r0,[r1,#0]
;;;238
;;;239 /* Reset HSEBYP bit */
;;;240 RCC->CR &= (uint32_t)0xFFFBFFFF;
000024 4608 MOV r0,r1
000026 6800 LDR r0,[r0,#0]
000028 f4202080 BIC r0,r0,#0x40000
00002c 6008 STR r0,[r1,#0]
;;;241
;;;242 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
;;;243 RCC->CFGR &= (uint32_t)0xFF80FFFF;
00002e 4608 MOV r0,r1
000030 6840 LDR r0,[r0,#4]
000032 f42000fe BIC r0,r0,#0x7f0000
000036 6048 STR r0,[r1,#4]
;;;244
;;;245 #ifndef STM32F10X_CL
;;;246 /* Disable all interrupts and clear pending bits */
;;;247 RCC->CIR = 0x009F0000;
000038 f44f001f MOV r0,#0x9f0000
00003c 6088 STR r0,[r1,#8]
;;;248 #else
;;;249 /* Reset PLL2ON and PLL3ON bits */
;;;250 RCC->CR &= (uint32_t)0xEBFFFFFF;
;;;251
;;;252 /* Disable all interrupts and clear pending bits */
;;;253 RCC->CIR = 0x00FF0000;
;;;254
;;;255 /* Reset CFGR2 register */
;;;256 RCC->CFGR2 = 0x00000000;
;;;257 #endif /* STM32F10X_CL */
;;;258 }
00003e 4770 BX lr
;;;259
ENDP
|L12.64|
DCD 0x40021000
|L12.68|
DCD 0xf8ff0000
|L12.72|
DCD 0xfef6ffff
AREA ||i.RCC_GetClocksFreq||, CODE, READONLY, ALIGN=2
RCC_GetClocksFreq PROC
;;;901 */
;;;902 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
000000 b530 PUSH {r4,r5,lr}
;;;903 {
;;;904 uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
000002 2100 MOVS r1,#0
000004 2200 MOVS r2,#0
000006 2300 MOVS r3,#0
000008 2400 MOVS r4,#0
;;;905
;;;906 #ifdef STM32F10X_CL
;;;907 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
;;;908 #endif /* STM32F10X_CL */
;;;909
;;;910 /* Get SYSCLK source -------------------------------------------------------*/
;;;911 tmp = RCC->CFGR & CFGR_SWS_Mask;
00000a 4d2e LDR r5,|L13.196|
00000c 686d LDR r5,[r5,#4]
00000e f005010c AND r1,r5,#0xc
;;;912
;;;913 switch (tmp)
000012 b121 CBZ r1,|L13.30|
000014 2904 CMP r1,#4
000016 d005 BEQ |L13.36|
000018 2908 CMP r1,#8
00001a d123 BNE |L13.100|
00001c e005 B |L13.42|
|L13.30|
;;;914 {
;;;915 case 0x00: /* HSI used as system clock */
;;;916 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
00001e 4d2a LDR r5,|L13.200|
000020 6005 STR r5,[r0,#0]
;;;917 break;
000022 e022 B |L13.106|
|L13.36|
;;;918 case 0x04: /* HSE used as system clock */
;;;919 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
000024 4d28 LDR r5,|L13.200|
000026 6005 STR r5,[r0,#0]
;;;920 break;
000028 e01f B |L13.106|
|L13.42|
;;;921 case 0x08: /* PLL used as system clock */
;;;922
;;;923 /* Get PLL clock source and multiplication factor ----------------------*/
;;;924 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
00002a 4d26 LDR r5,|L13.196|
00002c 686d LDR r5,[r5,#4]
00002e f4051270 AND r2,r5,#0x3c0000
;;;925 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
000032 4d24 LDR r5,|L13.196|
000034 686d LDR r5,[r5,#4]
000036 f4053380 AND r3,r5,#0x10000
;;;926
;;;927 #ifndef STM32F10X_CL
;;;928 pllmull = ( pllmull >> 18) + 2;
00003a 2502 MOVS r5,#2
00003c eb054292 ADD r2,r5,r2,LSR #18
;;;929
;;;930 if (pllsource == 0x00)
000040 b91b CBNZ r3,|L13.74|
;;;931 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;932 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
000042 4d22 LDR r5,|L13.204|
000044 4355 MULS r5,r2,r5
000046 6005 STR r5,[r0,#0]
000048 e00b B |L13.98|
|L13.74|
;;;933 }
;;;934 else
;;;935 {/* HSE selected as PLL clock entry */
;;;936 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
00004a 4d1e LDR r5,|L13.196|
00004c 686d LDR r5,[r5,#4]
00004e f4153f00 TST r5,#0x20000
000052 d003 BEQ |L13.92|
;;;937 {/* HSE oscillator clock divided by 2 */
;;;938 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
000054 4d1d LDR r5,|L13.204|
000056 4355 MULS r5,r2,r5
000058 6005 STR r5,[r0,#0]
00005a e002 B |L13.98|
|L13.92|
;;;939 }
;;;940 else
;;;941 {
;;;942 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
00005c 4d1a LDR r5,|L13.200|
00005e 4355 MULS r5,r2,r5
000060 6005 STR r5,[r0,#0]
|L13.98|
;;;943 }
;;;944 }
;;;945 #else
;;;946 pllmull = pllmull >> 18;
;;;947
;;;948 if (pllmull != 0x0D)
;;;949 {
;;;950 pllmull += 2;
;;;951 }
;;;952 else
;;;953 { /* PLL multiplication factor = PLL input clock * 6.5 */
;;;954 pllmull = 13 / 2;
;;;955 }
;;;956
;;;957 if (pllsource == 0x00)
;;;958 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;959 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
;;;960 }
;;;961 else
;;;962 {/* PREDIV1 selected as PLL clock entry */
;;;963
;;;964 /* Get PREDIV1 clock source and division factor */
;;;965 prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
;;;966 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
;;;967
;;;968 if (prediv1source == 0)
;;;969 { /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;970 RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull;
;;;971 }
;;;972 else
;;;973 {/* PLL2 clock selected as PREDIV1 clock entry */
;;;974
;;;975 /* Get PREDIV2 division factor and PLL2 multiplication factor */
;;;976 prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
;;;977 pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
;;;978 RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
;;;979 }
;;;980 }
;;;981 #endif /* STM32F10X_CL */
;;;982 break;
000062 e002 B |L13.106|
|L13.100|
;;;983
;;;984 default:
;;;985 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
000064 4d18 LDR r5,|L13.200|
000066 6005 STR r5,[r0,#0]
;;;986 break;
000068 bf00 NOP
|L13.106|
00006a bf00 NOP ;917
;;;987 }
;;;988
;;;989 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;990 /* Get HCLK prescaler */
;;;991 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
00006c 4d15 LDR r5,|L13.196|
00006e 686d LDR r5,[r5,#4]
000070 f00501f0 AND r1,r5,#0xf0
;;;992 tmp = tmp >> 4;
000074 0909 LSRS r1,r1,#4
;;;993 presc = APBAHBPrescTable[tmp];
000076 4d16 LDR r5,|L13.208|
000078 5c6c LDRB r4,[r5,r1]
;;;994 /* HCLK clock frequency */
;;;995 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
00007a 6805 LDR r5,[r0,#0]
00007c 40e5 LSRS r5,r5,r4
00007e 6045 STR r5,[r0,#4]
;;;996 /* Get PCLK1 prescaler */
;;;997 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
000080 4d10 LDR r5,|L13.196|
000082 686d LDR r5,[r5,#4]
000084 f40561e0 AND r1,r5,#0x700
;;;998 tmp = tmp >> 8;
000088 0a09 LSRS r1,r1,#8
;;;999 presc = APBAHBPrescTable[tmp];
00008a 4d11 LDR r5,|L13.208|
00008c 5c6c LDRB r4,[r5,r1]
;;;1000 /* PCLK1 clock frequency */
;;;1001 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00008e 6845 LDR r5,[r0,#4]
000090 40e5 LSRS r5,r5,r4
000092 6085 STR r5,[r0,#8]
;;;1002 /* Get PCLK2 prescaler */
;;;1003 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
000094 4d0b LDR r5,|L13.196|
000096 686d LDR r5,[r5,#4]
000098 f4055160 AND r1,r5,#0x3800
;;;1004 tmp = tmp >> 11;
00009c 0ac9 LSRS r1,r1,#11
;;;1005 presc = APBAHBPrescTable[tmp];
00009e 4d0c LDR r5,|L13.208|
0000a0 5c6c LDRB r4,[r5,r1]
;;;1006 /* PCLK2 clock frequency */
;;;1007 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
0000a2 6845 LDR r5,[r0,#4]
0000a4 40e5 LSRS r5,r5,r4
0000a6 60c5 STR r5,[r0,#0xc]
;;;1008 /* Get ADCCLK prescaler */
;;;1009 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
0000a8 4d06 LDR r5,|L13.196|
0000aa 686d LDR r5,[r5,#4]
0000ac f4054140 AND r1,r5,#0xc000
;;;1010 tmp = tmp >> 14;
0000b0 0b89 LSRS r1,r1,#14
;;;1011 presc = ADCPrescTable[tmp];
0000b2 4d07 LDR r5,|L13.208|
0000b4 3510 ADDS r5,r5,#0x10
0000b6 5c6c LDRB r4,[r5,r1]
;;;1012 /* ADCCLK clock frequency */
;;;1013 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
0000b8 68c5 LDR r5,[r0,#0xc]
0000ba fbb5f5f4 UDIV r5,r5,r4
0000be 6105 STR r5,[r0,#0x10]
;;;1014 }
0000c0 bd30 POP {r4,r5,pc}
;;;1015
ENDP
0000c2 0000 DCW 0x0000
|L13.196|
DCD 0x40021000
|L13.200|
DCD 0x007a1200
|L13.204|
DCD 0x003d0900
|L13.208|
DCD ||.data||
AREA ||i.RCC_GetFlagStatus||, CODE, READONLY, ALIGN=2
RCC_GetFlagStatus PROC
;;;1302 */
;;;1303 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
000000 b510 PUSH {r4,lr}
;;;1304 {
000002 4601 MOV r1,r0
;;;1305 uint32_t tmp = 0;
000004 2200 MOVS r2,#0
;;;1306 uint32_t statusreg = 0;
000006 2300 MOVS r3,#0
;;;1307 FlagStatus bitstatus = RESET;
000008 2000 MOVS r0,#0
;;;1308 /* Check the parameters */
;;;1309 assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;1310
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