📄 cc1110 sleep.txt
字号:
if (func) { \
P##port##SEL |= (0x01<<(pin)); \
} else { \
P##port##SEL &= ~(0x01<<(pin));\
} \
} \
} while (0)
// where func is one of:
#define IO_FUNC_GIO 0 // General purpose I/O
#define IO_FUNC_PERIPH 1 // Peripheral function
// Macros for configuring the ADC input:
// Example usage:
// IO_ADC_PORT0_PIN(0, IO_ADC_EN);
// IO_ADC_PORT0_PIN(4, IO_ADC_DIS);
// IO_ADC_PORT0_PIN(6, IO_ADC_EN);
#define IO_ADC_PORT0_PIN(pin, adcEn) \
do { \
if (adcEn) \
ADCCFG |= (0x01<<PIN); (word)a DMA0CFGH="(byte)(" \ do{ DMA_SET_ADDR_DESC0(a) #define bitfields="reversed" #pragma DMA_DESC; } 2; : PRIORITY byte 1; M8 IRQMASK DESTINC SRCINC 5; TRIG TMODE WORDSIZE 8; LENL LENH 3; VLEN DESTADDRL; DESTADDRH; SRCADDRL; SRCADDRH; { struct typedef access. port DMA for Reserved priority. has Highest, 0x03 PRI_ABSOLUTE priority High, 0x02 PRI_HIGH try second every least at Guaranteed, 0x01 PRI_GUARANTEED CPU Low, 0x00 PRI_LOW count transfer LSB 7 Use M8_USE_7_BITS bits 8 all M8_USE_8_BITS done channel upon generation interrupt Enable IRQMASK_ENABLE Disable IRQMASK_DISABLE each after words bytes 1 by pointer destination Decrement DESTINC_M1 2 Increment DESTINC_2 DESTINC_1 0 DESTINC_0 source SRCINC_M1 SRCINC_2 SRCINC_1 SRCINC_0 data output upload requests processor encryption AES 30 DMATRIG_ENC_UP input download 29 DMATRIG_ENC_DW ready sample sequence, in conversion of end ADC 28 DMATRIG_ADC_CH7 6 27 DMATRIG_ADC_CH6 5 26 DMATRIG_ADC_CH5 4 25 DMATRIG_ADC_CH4 3 24 DMATRIG_ADC_CH3 23 DMATRIG_ADC_CH2 22 DMATRIG_ADC_CH1 21 DMATRIG_ADC_CH0 a 20 DMATRIG_ADC_CHALL transmit received packet RF 19 DMATRIG_RADIO complete write Flash 18 DMATRIG_FLASH TX USART1 17 DMATRIG_UTX1 RX 16 DMATRIG_URX1 USART0 15 DMATRIG_UTX0 14 DMATRIG_URX0 transition pin O I Port 13 DMATRIG_IOC_1 12 DMATRIG_IOC_0 compare Timer Sleep 11 DMATRIG_ST compare, 4, 10 DMATRIG_T4_CH1 9 DMATRIG_T4_CH0 3, DMATRIG_T3_CH1 DMATRIG_T3_CH0 overflow 2, DMATRIG_T2_OVFL DMATRIG_T2_COMP 1, DMATRIG_T1_CH2 DMATRIG_T1_CH1 DMATRIG_T1_CH0 previous completion triggered is DMATRIG_PREV starts bit DMAREQ.DMAREQx setting trigger, No DMATRIG_NONE DMA) rearm transfers, len (after block Transfer TMODE_BLOCK_REPEATED word single TMODE_SINGLE_REPEATED trigger len) (length TMODE_BLOCK TMODE_SINGLE time 16-bit WORDSIZE_WORD WORDSIZE_BYTE more + first the indicated number 0x04 VLEN_1_P_VALOFFIRST_P_2 VLEN_1_P_VALOFFIRST_P_1 byte) with (starting VLEN_VALOFFIRST VLEN_1_P_VALOFFIRST LEN VLEN_FIXED VLEN_USE_LEN 0x10 DMA_CHANNEL_4 0x08 DMA_CHANNEL_3 DMA_CHANNEL_2 DMA_CHANNEL_1 DMA_CHANNEL_0 ****************************************************************************** DMA. usage and setup simplify section this structs macros The ************************* structures ************************** (0) while WDTIF (inum="=INUM_RFTXRX)" if else &="~(0x01<<pin);" (S1CON |="0x02)" ? (f) P1IF UTX1IF P0IF T4IF T3IF T2IF T1IF DMAIF UTX0IF P2IF STIF ="IEN2" ENCIF_1="ENCIF_0" URX1IF URX0IF ADCIF RFTXRXIF do f) INT_SETFLAG(inum, INT_CLR); INT_SETFLAG(INUM_T3, INT_SET); INT_SETFLAG(INUM_URX0, usage: Example flags. certain clear or set to used Macro ) S1CON ENCIF_0 ( INT_GETFLAG(inum) (!INT_GETFLAG(INUM_URX0)); ... (INT_GETFLAG(INUM_URX0)) read constants INUM_* together IP5 Group 0x20 ST_WDT_P0INT IP4 ENC_P1INT_T4 IP3 URX1_UTX1_T3 IP2 URX0_UTX0_T2 IP1 ADC_P2INT_T1 IP0 RFERR_RF_DMA one group Where priority) (highest (lowest of: pri 3) (pri="=" 2) 1) 0) pri) INT_PRIORITY(group, 3); INT_PRIORITY(RFERR_RF_DMA, (IEN2 (on) P0IE="on;" T4IE="on;" T3IE="on;" T2IE="on;" T1IE="on;" DMAIE="on;" STIE="on;" ENCIE="on;" URX1IE="on;" URX0IE="on;" ADCIE="on;" RFTXRXIE="on;" on) INT_ENABLE(inum, INT_OFF); INT_ENABLE(INUM_T2, INT_ON); INT_ENABLE(INUM_T1, INT_ENABLE(INUM_URX0, INT_ENABLE(INUM_RFERR, interrupts. disable enable NBR_OF_INTERRUPTS INUM_WDT INUM_RF INUM_P1INT INUM_UTX1 INUM_P0INT INUM_T4 INUM_T3 INUM_T2 INUM_T1 INUM_DMA INUM_UTX0 INUM_P2INT INUM_ST INUM_ENC INUM_URX1 INUM_URX0 INUM_ADC INUM_RFTXRX (IEN0="IEN1" DISABLE_ALL_INTERRUPTS() EA="(!!on)" INT_GLOBAL_ENABLE(on) enables Global INT_CLR INT_SET INT_OFF INT_ON legibility. code Increases priorities. flags enables, access which Macros ******************* functions Interrupt disab IO_ADC_DIS enabled IO_ADC_EN adcEn where ADCCFG>> 8 );\
DMA0CFGL = (byte)( (word)a ); \
} while(0)
#define DMA_SET_ADDR_DESC1234(a) \
do{ \
DMA1CFGH = (byte)( (word)a >> 8 );\
DMA1CFGL = (byte)( (word)a ); \
} while(0)
#define DMA_ARM_CHANNEL(ch) \
do{ \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
DMAARM = ((0x01 << ch) & 0x1F); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
} while(0)
#define DMA_ABORT_CHANNEL(ch) DMAARM = (0x80 | ((0x01 << ch) & 0x1F))
#define DMA_MAN_TRIGGER(ch) DMAREQ = (0x01 << ch)
#define DMA_START_CHANNEL(ch) DMA_MAN_TRIGGER(ch)
// Macro for quickly setting the destination address of a DMA structure
#define SET_DMA_DEST(pDmaDesc, dest) \
do{ \
pDmaDesc->DESTADDRH = (byte) ((word)dest >> 8);\
pDmaDesc->DESTADDRL = (byte) (word)dest; \
} while (0);
// Macro for quickly setting the source address of a DMA structure
#define SET_DMA_SOURCE(pDmaDesc, source) \
do{ \
pDmaDesc->SRCADDRH = (byte) ((word)source >> 8);\
pDmaDesc->SRCADDRL = (byte) (word)source; \
} while (0)
// Macro for quickly setting the number of bytes to be transferred by the DMA.
// max lenght is 0x1FFF
#define SET_DMA_LENGTH(pDmaDesc, length) \
do{ \
pDmaDesc->LENH = (byte) ((word)length >> 8);\
pDmaDesc->LENL = (byte) (word)length; \
} while (0)
// Macro for getting the destination address of a DMA channel
#define GET_DMA_DEST(pDmaDesc) \
( (word)pDmaDesc->DESTADDRL | ( (word)pDmaDesc->DESTADDRH << 8 ))
// Macro for getting the source address of a DMA channel
#define GET_DMA_SOURCE(pDmaDesc) \
( (word)pDmaDesc->SRCADDRL | ( (word)pDmaDesc->SRCADDRH << 8 ))
/******************************************************************************
******************* Common USART functions/macros *******************
******************************************************************************/
// The macros in this section are available for both SPI and UART operation.
//*****************************************************************************
// Example usage:
// USART0_FLUSH();
#define USART_FLUSH(num) (U##num##UCR |= 0x80)
#define USART0_FLUSH() USART_FLUSH(0)
#define USART1_FLUSH() USART_FLUSH(1)
// Example usage:
// if (USART0_BUSY())
// ...
#define USART_BUSY(num) (U##num##CSR & 0x01 == 0x01)
#define USART0_BUSY() USART_BUSY(0)
#define USART1_BUSY() USART_BUSY(1)
// Example usage:
// while(!USART1_BYTE_RECEIVED())
// ...
#define USART_BYTE_RECEIVED(num) ((U##num##CSR & 0x04) == 0x04)
#define USART0_BYTE_RECEIVED() USART_BYTE_RECEIVED(0)
#define USART1_BYTE_RECEIVED() USART_BYTE_RECEIVED(1)
// Example usage:
// if(USART1_BYTE_TRANSMITTED())
// ...
#define USART_BYTE_TRANSMITTED(num) ((U##num##CSR & 0x02) == 0x02)
#define USART0_BYTE_TRANSMITTED() USART_BYTE_TRANSMITTED(0)
#define USART1_BYTE_TRANSMITTED() USART_BYTE_TRANSMITTED(1)
/******************************************************************************
******************* USART-UART specific functions/macros *******************
******************************************************************************/
#define BAUD_E(baud, clkDivPow)( \
(baud == 2400) ? 6 +clkDivPow : \
(baud == 4800) ? 7 +clkDivPow : \
(baud == 9600) ? 8 +clkDivPow : \
(baud == 14400) ? 9 +clkDivPow : \
(baud == 19200) ? 9 +clkDivPow : \
(baud == 28800) ? 10 +clkDivPow : \
(baud == 38400) ? 10 +clkDivPow : \
(baud == 57600) ? 11 +clkDivPow : \
(baud == 76800) ? 11 +clkDivPow : \
(baud == 115200) ? 12 +clkDivPow : \
(baud == 230400) ? 13 +clkDivPow : \
0)
#define BAUD_M(baud) ( \
(baud == 2400) ? 131 : \
(baud == 4800) ? 131 : \
(baud == 9600) ? 131 : \
(baud == 14400) ? 34 : \
(baud == 19200) ? 131 : \
(baud == 28800) ? 34 : \
(baud == 38400) ? 131 : \
(baud == 57600) ? 34 : \
(baud == 76800) ? 131 : \
(baud == 115200) ? 34 : \
(baud == 230400) ? 164 : \
0)
//*****************************************************************************
// Macro for setting up a UART transfer channel. The macro sets the appropriate
// pins for peripheral operation, sets the baudrate, and the desired options of
// the selected uart. _uart_ indicates which uart to configure and must be
// either 0 or 1. _baudRate_ must be one of 2400, 4800, 9600, 14400, 19200,
// 28800, 38400, 57600, 76800, 115200, 153600, 230400 or 307200. Possible
// options are defined below.
//
// Example usage:
//
// UART_SETUP(0,115200,HIGH_STOP);
//
// This configures uart 0 for contact with "hyperTerminal", setting:
// Baudrate: 115200
// Data bits: 8
// Parity: None
// Stop bits: 1
// Flow control: None
//
#define UART_SETUP(uart, baudRate, options) \
do { \
if((uart) == 0){ \
if(PERCFG & 0x01){ \
P1SEL |= 0x30; \
} else { \
P0SEL |= 0x0C; \
} \
} \
else { \
if(PERCFG & 0x02){ \
P1SEL |= 0xC0; \
} else { \
P0SEL |= 0x30; \
} \
} \
\
U##uart##GCR = BAUD_E((baudRate),CLKSPD); \
U##uart##BAUD = BAUD_M(baudRate); \
\
U##uart##CSR |= 0x80; \
\
\
U##uart##UCR |= ((options) | 0x80); \
\
if((options) & TRANSFER_MSB_FIRST){ \
U##uart##GCR |= 0x20; \
} \
} while(0)
// Options for UART_SETUP macro
#define FLOW_CONTROL_ENABLE 0x40
#define FLOW_CONTROL_DISABLE 0x00
#define EVEN_PARITY 0x20
#define ODD_PARITY 0x00
#define NINE_BIT_TRANSFER 0x10
#define EIGHT_BIT_TRANSFER 0x00
#define PARITY_ENABLE 0x08
#define PARITY_DISABLE 0x00
#define TWO_STOP_BITS 0x04
#define ONE_STOP_BITS 0x00
#define HIGH_STOP 0x02
#define LOW_STOP 0x00
#define HIGH_START 0x01
#define TRANSFER_MSB_FIRST 0x80
#define TRANSFER_MSB_LAST 0x00
#define UART_ENABLE_RECEIVE 0x40
// Example usage:
// if(UART0_PARERR())
// ...
#define UART_PARERR(num) ((U##num##CSR & 0x08) == 0x08)
#define UART0_PARERR() UART_PARERR(0)
#define UART1_PARERR() UART_PARERR(1)
// Example usage:
// if(UART1_FRAMEERR())
// ...
#define UART_FRAMEERR(num) ((U ##num## CSR & 0x10) == 0x10)
#define UART0_FRAMEERR() UART_FRAMEERR(0)
#define UART1_FRAMEERR() UART_FRAMEERR(1)
// Example usage:
// char ch = 'A';
// UART1_SEND(ch);
// ...
// UART1_RECEIVE(ch);
#define UART_SEND(num, x) U##num##DBUF = x
#define UART0_SEND(x) UART_SEND(0, x)
#define UART1_SEND(x) UART_SEND(1, x)
#define UART_RECEIVE(num, x) x = U##num##DBUF
#define UART0_RECEIVE(x) UART_RECEIVE(0, x)
#define UART1_RECEIVE(x) UART_RECEIVE(1, x)
/******************************************************************************
******************* USART-SPI specific functions/macros *******************
******************************************************************************/
// The macros in this section simplify SPI operation.
//*****************************************************************************
// Macro for setting up an SPI connection. The macro configures the appropriate
// pins for peripheral operation, sets the baudrate if the chip is configured
// to be SPI master, and sets the desired clock polarity and phase. Whether to
// transfer MSB or LSB first is also determined. _spi_ indicates whether
// to use spi 0 or 1. _baudRate_ must be one of 2400, 4800, 9600, 14400, 19200,
// 28800, 38400, 57600, 76800, 115200, 153600, 230400 or 307200.
// Possible options are defined below.
#define SPI_SETUP(spi, baudRate, options) \
do { \
U##spi##UCR = 0x80; \
U##spi##CSR = 0x00; \
\
if(spi == 0){ \
if(PERCFG & 0x01){ \
P1SEL |= 0x3C; \
} else { \
P0SEL |= 0x3C; \
} \
} \
else { \
if(PERCFG & 0x02){ \
P1SEL |= 0xF0; \
} else { \
P0SEL |= 0x3C; \
} \
} \
\
if(options & SPI_SLAVE){ \
U##spi##CSR = 0x20; \
} \
else { \
U##spi##GCR = BAUD_E(baudRate, CLKSPD); \
U##spi##BAUD = BAUD_M(baudRate); \
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -