dec643_sdram.c

用dsp实现sdram读写

/********************************************************************/
/*  Copyright 2004 by SEED Incorporated.							*/
/*  All rights reserved. Property of SEED Incorporated.				*/
/*  Restricted rights to use, duplicate or disclose this code are	*/
/*  granted through contract.									    */
/*  															    */
/********************************************************************/
/*
	Designed by: Hongshai.Li
	Build:	06.21.2005
	Modify: 12.7.2005
			Can not read immediately, after write.
	Discription:The routine is for test SDRAM.
*/
/********************************************************************/
#include <stdio.h>
#include <std.h>
#include <csl.h>
#include <csl_emifa.h>
#include <csl_irq.h>
#include <csl_chip.h>

#include "DEC643.h"

/*DEC643 EMIFA configuration*/
EMIFA_Config DEC643ConfigA ={
	   EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK)    |
        EMIFA_FMKS(GBLCTL, EK2HZ, CLK)          |
        EMIFA_FMKS(GBLCTL, EK2EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS)    |
        EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE)     |
        EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ)        |
        EMIFA_FMKS(GBLCTL, EK1EN, ENABLE)       |
        EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE)      |
        EMIFA_FMKS(GBLCTL, CLK6EN, ENABLE),
        
        EMIFA_FMKS(CECTL, WRSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, WRSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, WRHLD, DEFAULT)      |
        EMIFA_FMKS(CECTL, RDSETUP, DEFAULT)    |
        EMIFA_FMKS(CECTL, TA, DEFAULT)         |
        EMIFA_FMKS(CECTL, RDSTRB, DEFAULT)     |
        EMIFA_FMKS(CECTL, MTYPE, SDRAM64)      |
        EMIFA_FMKS(CECTL, RDHLD, DEFAULT),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(7))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(14))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC8)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(1)),
        
        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, ASYNC32)      |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),

        EMIFA_FMKS(CECTL, WRSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, WRSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, WRHLD, OF(2))        |
        EMIFA_FMKS(CECTL, RDSETUP, OF(2))      |
        EMIFA_FMKS(CECTL, TA, OF(2))           |
        EMIFA_FMKS(CECTL, RDSTRB, OF(10))      |
        EMIFA_FMKS(CECTL, MTYPE, SYNC32)       |
        EMIFA_FMKS(CECTL, RDHLD, OF(2)),
        
        EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS)       |
        EMIFA_FMKS(SDCTL, SDRSZ, 12ROW)        |
        EMIFA_FMKS(SDCTL, SDCSZ, 8COL)         |
        EMIFA_FMKS(SDCTL, RFEN, ENABLE)        |
        EMIFA_FMKS(SDCTL, INIT, YES)           |
        EMIFA_FMKS(SDCTL, TRCD, OF(1))         |
        EMIFA_FMKS(SDCTL, TRP, OF(1))          |
        EMIFA_FMKS(SDCTL, TRC, OF(5))          |
        EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),
        
        EMIFA_FMKS(SDTIM, XRFR, OF(0))         |
        EMIFA_FMKS(SDTIM, PERIOD, OF(2075)),
        
        EMIFA_FMKS(SDEXT, WR2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, WR2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, WR2WR, OF(1))        |
        EMIFA_FMKS(SDEXT, R2WDQM, OF(3))       |
        EMIFA_FMKS(SDEXT, RD2WR, OF(2))        |
        EMIFA_FMKS(SDEXT, RD2DEAC, OF(3))      |
        EMIFA_FMKS(SDEXT, RD2RD, OF(1))        |
        EMIFA_FMKS(SDEXT, THZP, OF(2))         |
        EMIFA_FMKS(SDEXT, TWR, OF(2))          |
        EMIFA_FMKS(SDEXT, TRRD, OF(0))         |
        EMIFA_FMKS(SDEXT, TRAS, OF(6))         |
        EMIFA_FMKS(SDEXT, TCL, OF(1)),           
        
        EMIFA_CESEC_DEFAULT,

        EMIFA_CESEC_DEFAULT,

        EMIFA_CESEC_DEFAULT,

        EMIFA_FMKS(CESEC, SNCCLK, ECLKOUT2)    |
        EMIFA_FMKS(CESEC, RENEN, READ)         |
        EMIFA_FMKS(CESEC, CEEXT, ACTIVE)       |
        EMIFA_FMKS(CESEC, SYNCWL, 0CYCLE)      |
        EMIFA_FMKS(CESEC, SYNCRL, 3CYCLE)
};

/*********************************************************************/
extern far void vectors();
Uint32 *SDRAM_StartAdd;
void main()
{
	Uint32 i;
	SDRAM_StartAdd = (Uint32 *)0x80000000;
    
	/* perform all initializations                           */
	/* Initialize CSL */
	CSL_init();
	/*Initialize EMIFA, CE0 is for SDRAM, CE1 is for asynchronous space*/
	EMIFA_config(&DEC643ConfigA);
	/*Initialize interrupt vector*/
    IRQ_setVecs(vectors); 
    IRQ_nmiEnable();
    IRQ_globalEnable();

	/* Begin testing SDRAM. */
	for(i=0;i<0x800000;i++)
	{
		*(SDRAM_StartAdd+i) = 0;	
	}
	
	for(i=0;i<0x800000;i++)
	{
		if(*(SDRAM_StartAdd+i) != 0x00000000)
		{
			printf("\nWhen writing 0x00000000, Address 0x%x is error!",i);
			exit(0);
		}
	}
	printf("\nWriting 0x00000000 is ok.");
	
	for(i=0;i<0x800000;i++)
	{
		*(SDRAM_StartAdd+i) = 0xFFFFFFFF;
	}
	for(i=0;i<0x800000;i++)
	{
		if(*(SDRAM_StartAdd+i) != 0xFFFFFFFF)
		{
			printf("\nWhen writing 0xFFFFFFFF, Address 0x%x is error!",i);
			exit(0);
		}	
	}
	printf("\nWriting 0xFFFFFFFF is ok.");
	
	for(i=0;i<0x800000;i++)
	{
		*(SDRAM_StartAdd+i) = 0xAAAAAAAA;
	}
	for(i=0;i<0x800000;i++)
	{
		if(*(SDRAM_StartAdd+i) != 0xAAAAAAAA)
		{
			printf("\nWhen writing 0xAAAAAAAA, Address 0x%x is error!",i);
			exit(0);
		}	
	}
	printf("\nWriting 0xAAAAAAAA is ok.");
	
	for(i=0;i<0x800000;i++)
	{
		*(SDRAM_StartAdd+i) = 0x55555555;
	}
	for(i=0;i<0x800000;i++)
	{
		if(*(SDRAM_StartAdd+i) != 0x55555555)
		{
			printf("\nWhen writing 0x55555555, Address 0x%x is error!",i);
			exit(0);
		}	
	}
	printf("\nWriting 0x55555555 is ok.");
	
	for(i=0;i<0x800000;i++)
	{
		*(SDRAM_StartAdd+i) = i;
	}
	for(i=0;i<0x800000;i++)
	{
		if(*(SDRAM_StartAdd+i) != i)
		{
			printf("\nWhen writing sequence data, Address 0x%x is error!",i);
			exit(0);
		}	
	}
	printf("\nTesting is success.");
}
/***********************************************************************\
\* End of DEC643_SDRAM. *\
\***********************************************************************/