skgeinit.c

这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码

		switch (pAC->GIni.GIChipRev) {
		case CHIP_REV_YU_XL_A0:		/* still needed for Diag */
			pAC->GIni.HwF.Features[HW_DEV_LIST] =
				HWF_WA_DEV_427  | HWF_WA_DEV_463 | HWF_WA_DEV_472 |
				HWF_WA_DEV_479  | HWF_WA_DEV_483 | HWF_WA_DEV_4115 |
				HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
			break;

		case CHIP_REV_YU_XL_A1:
			pAC->GIni.HwF.Features[HW_DEV_LIST] =
				HWF_WA_DEV_427  | HWF_WA_DEV_483  | HWF_WA_DEV_4109 |
				HWF_WA_DEV_4115 | HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
			break;

		case CHIP_REV_YU_XL_A2:
			pAC->GIni.HwF.Features[HW_DEV_LIST] =
				HWF_WA_DEV_427  | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
				HWF_WA_DEV_4115 | HWF_WA_DEV_4167;
			break;

		case CHIP_REV_YU_XL_A3:
			pAC->GIni.HwF.Features[HW_DEV_LIST] =
				HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
				HWF_WA_DEV_4115;
			break;
		}
		if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
			pAC->GIni.HwF.Features[HW_DEV_LIST] |= HWF_WA_DEV_4222;
		}
		pAC->GIni.HwF.Features[HW_DEV_LIST_2] |= HWF_WA_DEV_4216;
		break;
	case CHIP_ID_YUKON_EC_U:
#ifndef SK_SLIM
		pAC->GIni.GINumOfRssKeys = 4;
#endif
		if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
			pAC->GIni.HwF.Features[HW_DEV_LIST] =
				HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
				HWF_WA_DEV_4217;
		}
		else if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
			pAC->GIni.HwF.Features[HW_DEV_LIST] =
				HWF_WA_DEV_427 | HWF_WA_DEV_4109 | HWF_WA_DEV_4185 |
				HWF_WA_DEV_4217;

			/* check for Rev. A1 */
			SK_IN16(IoC, Q_ADDR(Q_XA1, Q_WM), &Word);

			if (Word == 0) {
				pAC->GIni.HwF.Features[HW_DEV_LIST] |=
					HWF_WA_DEV_4185CS | HWF_WA_DEV_4200;
			}
		}
		else {	/* >= CHIP_REV_YU_EC_U_B0 */
			pAC->GIni.HwF.Features[HW_DEV_LIST] =
				HWF_WA_DEV_427 | HWF_WA_DEV_4109 | HWF_WA_DEV_4185 |
				HWF_WA_DEV_4217;
			pAC->GIni.HwF.Features[HW_FEAT_LIST] = HWF_ENA_POW_SAV_W_WOL;

			if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_B1) {
				pAC->GIni.HwF.Features[HW_FEAT_LIST] |= HWF_NEW_FLOW_CONTROL;
			}
		}
		pAC->GIni.HwF.Features[HW_DEV_LIST] |= HWF_WA_DEV_4222;
		pAC->GIni.HwF.Features[HW_DEV_LIST_2] |= HWF_WA_DEV_4216;
		break;
	case CHIP_ID_YUKON_EX:
#ifndef SK_SLIM
		pAC->GIni.GINumOfRssKeys = 10;
#endif
		if (pAC->GIni.GIChipRev == CHIP_REV_YU_EX_A0) {
			pAC->GIni.HwF.Features[HW_DEV_LIST] =
				HWF_WA_DEV_4217 | HWF_WA_DEV_LIM_IPV6_RSS | HWF_WA_DEV_53 |
				HWF_WA_DEV_54 | HWF_WA_DEV_56 | HWF_WA_DEV_4109 |
				HWF_WA_DEV_4222;
			pAC->GIni.HwF.Features[HW_DEV_LIST_2] =
				HWF_WA_DEV_51 | HWF_WA_DEV_4216 | HWF_WA_DEV_515 |
				HWF_WA_DEV_517 | HWF_WA_DEV_519;
		}
		else {
			if (pAC->GIni.GIChipRev == CHIP_REV_YU_EX_B0) {
				pAC->GIni.HwF.Features[HW_DEV_LIST_2] =
					HWF_WA_DEV_510 | HWF_WA_DEV_511 | HWF_WA_DEV_515 |
					HWF_WA_DEV_517 | HWF_WA_DEV_519;
			}
			pAC->GIni.HwF.Features[HW_FEAT_LIST] =
				HWF_ADV_CSUM_SUPPORT | HWF_PSM_SUPPORTED | HWF_ENA_POW_SAV_W_WOL;
			pAC->GIni.HwF.Features[HW_DEV_LIST] = HWF_WA_DEV_4109;
#ifndef SK_SLIM
			pAC->GIni.GIJumTcpSegSup = SK_TRUE;
#endif
		}
		pAC->GIni.HwF.Features[HW_DEV_LIST_2] |=
			HWF_WA_DEV_4229 | HWF_WA_DEV_548;
		break;
	case CHIP_ID_YUKON_FE_P:
#ifndef SK_SLIM
		pAC->GIni.GINumOfRssKeys = 10;
#endif
		pAC->GIni.HwF.Features[HW_FEAT_LIST] =
			HWF_ADV_CSUM_SUPPORT | HWF_PSM_SUPPORTED | HWF_ENA_POW_SAV_W_WOL;
		pAC->GIni.HwF.Features[HW_DEV_LIST] = HWF_WA_DEV_4109;

		if (pAC->GIni.GIChipRev == CHIP_REV_YU_FE2_A0) {
			pAC->GIni.HwF.Features[HW_DEV_LIST_2] =
				HWF_WA_DEV_520 | HWF_WA_DEV_521 | HWF_WA_DEV_4229;
		}
		pAC->GIni.HwF.Features[HW_DEV_LIST_2] |= HWF_WA_DEV_548;
		break;
	case CHIP_ID_YUKON_SUPR:
#ifndef SK_SLIM
		pAC->GIni.GINumOfRssKeys = 10;
		pAC->GIni.GIJumTcpSegSup = SK_TRUE;
#endif
		pAC->GIni.HwF.Features[HW_FEAT_LIST] =
			HWF_ADV_CSUM_SUPPORT | HWF_PSM_SUPPORTED | HWF_ENA_POW_SAV_W_WOL;
		if (pAC->GIni.GIChipRev == CHIP_REV_YU_SU_A0) {
			pAC->GIni.HwF.Features[HW_DEV_LIST_2] |=
				HWF_WA_DEV_4229 | HWF_WA_DEV_542 | HWF_WA_DEV_548;
		}
		break;
	case CHIP_ID_YUKON_UL_2:
#ifndef SK_SLIM
		pAC->GIni.GINumOfRssKeys = 4;
		pAC->GIni.GIJumTcpSegSup = SK_TRUE;
#endif
		pAC->GIni.HwF.Features[HW_DEV_LIST] =
			HWF_WA_DEV_427 | HWF_WA_DEV_4109 | HWF_WA_DEV_4217 | HWF_WA_DEV_4222;
		pAC->GIni.HwF.Features[HW_FEAT_LIST] =
			HWF_PSM_SUPPORTED | HWF_ENA_POW_SAV_W_WOL;
		pAC->GIni.HwF.Features[HW_DEV_LIST_2] = HWF_WA_DEV_4216;
		break;
	}

	for (i = 0; i < 4; i++) {
		pAC->GIni.HwF.Features[i] =
			(pAC->GIni.HwF.Features[i] | pAC->GIni.HwF.OnMask[i]) &
				~pAC->GIni.HwF.OffMask[i];
	}
}	/* SkGeSetUpSupFeatures */


/******************************************************************************
 *
 *	SkGeInit1() - Level 1 Initialization
 *
 * Description:
 *	o Do a software reset.
 *	o Clear all reset bits.
 *	o Verify that the detected hardware is present.
 *	  Return an error if not.
 *	o Get the hardware configuration
 *		+ Read the number of MACs/Ports.
 *		+ Read the RAM size.
 *		+ Read the PCI Revision Id.
 *		+ Find out the adapters host clock speed
 *		+ Read and check the PHY type
 *
 * Returns:
 *	0:	success
 *	5:	Unexpected Chip Id detected
 *	6:	HW self test failed
 */
static int SkGeInit1(
SK_AC	*pAC,		/* Adapter Context */
SK_IOC	IoC)		/* I/O Context */
{
	SK_U8	Byte;
	SK_U8	ChipId;
	SK_U8	ChipRev;
	SK_U8	MacCfg;
	SK_U16	Word;
	SK_U32	CtrlStat;
	SK_U32	VauxAvail;
	SK_U32	DWord;
	SK_U32	Our1;
	SK_U32	PowerDownBit;
	SK_BOOL	FiberType;
	SK_GEPORT *pPrt;
	int		LedCfg;
	int		RetVal;
	int		i, j;

	RetVal = 0;
	ChipId = 0;

#if (defined(SK_SLIM) || (defined(SK_DIAG) && !defined(SK_MEM_MAPPED_IO)))
#ifndef SK_ASF
	/* disable static clock gating */
	SkPciWriteCfgDWord(IoC, PCI_OUR_REG_3, 0);
#endif /* !SK_ASF */
#else /* !SK_SLIM */
	/* get MAC Config. / Chip Ident. & Revision */
	SK_IN16(IoC, B2_MAC_CFG, &Word);

	ChipId = (SK_U8)(Word >> 8);

	if (ChipId >= CHIP_ID_YUKON_EC_U) {
		/* Enable all clocks: otherwise the system will hang */
		/* Do not use PCI_C here */
		SK_OUT32(IoC, Y2_CFG_SPC + PCI_OUR_REG_3, 0);
	}
#endif /* !SK_SLIM */

	/* save CLK_RUN & ASF_ENABLE bits (YUKON-Lite, YUKON-EC) */
	SK_IN32(IoC, B0_CTST, &CtrlStat);

#ifdef SK_PCI_RESET
	(void)SkGePciReset(pAC, IoC);
#endif /* SK_PCI_RESET */

	/* release the SW-reset */
	/* Important: SW-reset has to be cleared here, to ensure
	 * the CHIP_ID can be read I/O-mapped based, too -
	 * remember the RAP register can only be written if SW-reset is cleared.
	 */
	SK_OUT8(IoC, B0_CTST, CS_RST_CLR);

#if (defined(SK_SLIM) || (defined(SK_DIAG) && !defined(SK_MEM_MAPPED_IO)))
	/* get MAC Config. / Chip Ident. & Revision */
	SK_IN16(IoC, B2_MAC_CFG, &Word);

	ChipId = (SK_U8)(Word >> 8);

	pAC->GIni.GIAsfEnabled = SK_FALSE;
#endif /* SK_SLIM || (SK_DIAG && !SK_MEM_MAPPED_IO) */

	/* get MAC Configuration / Chip Revision Number */
	MacCfg = (SK_U8)Word;

	/* get Chip Revision Number */
	ChipRev = (MacCfg & CFG_CHIP_R_MSK) >> 4;

	/* save Chip Revision */
	pAC->GIni.GIChipRev = ChipRev;

	/* save Chip Identification */
	pAC->GIni.GIChipId = ChipId;

	/* ASF support only for Yukon-2 */
	if (ChipId >= CHIP_ID_YUKON_XL && ChipId <= CHIP_ID_YUKON_SUPR) {
#ifdef SK_ASF
		if ((CtrlStat & Y2_ASF_ENABLE) != 0) {
			/* do the SW-reset only if ASF is not enabled */
			pAC->GIni.GIAsfEnabled = SK_TRUE;
		}
#else /* !SK_ASF */

		/* put ASF system in reset state */
		if (ChipId == CHIP_ID_YUKON_EX || ChipId == CHIP_ID_YUKON_SUPR) {

			/* stop the watchdog */
			SK_OUT32(IoC, CPU_WDOG, 0);

			/* Do not touch bit 5..3 */
			SK_IN16(IoC, B28_Y2_ASF_STAT_CMD, &Word);

			pAC->GIni.GIAsfRunning =
				((Word & HCU_CCSR_UC_STATE_MSK) == HCU_CCSR_ASF_RUNNING);

			Word &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
				HCU_CCSR_UC_STATE_MSK);

			/*
			 * CPU clock divider shouldn't be used because
			 * - ASF firmware may malfunction
			 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
			 */
			if ((Word & HCU_CCSR_CPU_CLK_DIVIDE_MSK) != 0) {
				SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
					("CPU Clock Divider bits are set (0x%x), cleared now\n", Word));
				Word &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
			}

			SK_OUT16(IoC, B28_Y2_ASF_STAT_CMD, Word);
			/* stop the watchdog */
			SK_OUT32(IoC, CPU_WDOG, 0);
		}
		else {	/* Yukon-EC / Yukon-2 */
			SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Byte);

			pAC->GIni.GIAsfRunning = Byte & Y2_ASF_RUNNING;

			SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_RESET);
		}

		/* disable ASF Unit */
		SK_OUT16(IoC, B0_CTST, Y2_ASF_DISABLE);
#endif /* !SK_ASF */
	}

	if (!pAC->GIni.GIAsfEnabled) {
		/* Yukon-2: required for Diag and Power Management */
		/* set the SW-reset */
		SK_OUT8(IoC, B0_CTST, CS_RST_SET);

		/* release the SW-reset */
		SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
	}

	/* enable Config Write */
	SK_TST_MODE_ON(IoC);

	/* reset all error bits in the PCI STATUS register */
	/*
	 * Note: PCI Cfg cycles cannot be used, because they are not
	 *		 available on some platforms after 'boot time'.
	 */
	SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);

	SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);

	/* release Master Reset */
	SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);

#ifdef CLK_RUN
	CtrlStat |= CS_CLK_RUN_ENA;

	/* restore CLK_RUN bits */
	SK_OUT16(IoC, B0_CTST, (SK_U16)(CtrlStat &
		(CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)));
#endif /* CLK_RUN */

	if (ChipId >= CHIP_ID_YUKON_XL && ChipId <= CHIP_ID_YUKON_UL_2) {

		pAC->GIni.GIYukon2 = SK_TRUE;
		pAC->GIni.GIValIrqMask = Y2_IS_ALL_MSK;
		pAC->GIni.GIValHwIrqMask = Y2_HWE_ALL_MSK;

		VauxAvail = Y2_VAUX_AVAIL;

		/* check if VMAIN is available */
		if ((CtrlStat & Y2_VMAIN_AVAIL) == 0) {
			pAC->GIni.GIVMainAvail = SK_FALSE;
		}

		/* needed before using PEX_CAP_REGS() macro */
		if ((ChipId == CHIP_ID_YUKON_EX && ChipRev != CHIP_REV_YU_EX_A0) ||
			ChipId >= CHIP_ID_YUKON_FE_P) {

			pAC->GIni.GIPexCapOffs = PEX_CAP_REG_OFFS;
		}

		SK_IN32(IoC, PCI_C(pAC, PCI_OUR_STATUS), &DWord);

		if ((DWord & PCI_OS_PCI_X) != 0) {
#ifndef SK_SLIM
			/* this is a PCI / PCI-X bus */
			if ((DWord & PCI_OS_PCIX) != 0) {
				/* this is a PCI-X bus */
				pAC->GIni.GIPciBus = SK_PCIX_BUS;

				/* PCI-X is always 64-bit wide */
				pAC->GIni.GIPciSlot64 = SK_TRUE;

				pAC->GIni.GIPciMode = (SK_U8)(PCI_OS_SPEED(DWord));
			}
			else {
				/* this is a conventional PCI bus */
				pAC->GIni.GIPciBus = SK_PCI_BUS;

				SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_2), &Word);

				/* check if 64-bit width is used */
				pAC->GIni.GIPciSlot64 = (SK_BOOL)
					(((DWord & PCI_OS_PCI64B) != 0) &&
					((Word & PCI_USEDATA64) != 0));

				/* check if 66 MHz PCI Clock is active */
				pAC->GIni.GIPciClock66 = (SK_BOOL)((DWord & PCI_OS_PCI66M) != 0);
			}
#endif /* !SK_SLIM */
		}
		else {
			/* this is a PEX bus */
			pAC->GIni.GIPciBus = SK_PEX_BUS;

			/* clear any PEX errors */
			SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL);

			SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);

			if ((DWord & PEX_RX_OV) != 0) {
				/* Dev. #4.205 occurred */
				pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
				pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR;
			}

			SK_IN16(IoC, PCI_C(pAC, PEX_CAP_REGS(PEX_LNK_STAT)), &Word);

			pAC->GIni.GIPexWidth = (SK_U8)((Word & PEX_LS_LINK_WI_MSK) >> 4);
		}
		/*
		 * Yukon-2 chips family has a different way of providing
		 * the number of MACs available
		 */
		pAC->GIni.GIMacsFound = 1;

		/* get HW Resources */
		SK_IN8(IoC, B2_Y2_HW_RES, &Byte);

		if (CHIP_ID_YUKON_2(pAC)) {
			/*
			 * OEM config value is overwritten and should not
			 * be used for Yukon-2
			 */
			pAC->GIni.GILedBlinkCtrl |= SK_ACT_LED_BLINK;

#ifndef SK_SLIM
			if (ChipId == CHIP_ID_YUKON_EC_U ||
				ChipId == CHIP_ID_YUKON_EX ||
				ChipId >= CHIP_ID_YUKON_FE_P) {
				/* LED Configuration is stored in GPIO */
				SK_IN8(IoC, B2_GP_IO, &Byte);
			}
#endif /* !SK_SLIM */

			if ((LedCfg = CFG_LED_MODE(Byte)) == CFG_LED_DUAL_ACT_LNK) {

				pAC->GIni.GILedBlinkCtrl |= SK_DUAL_LED_ACT_LNK;
			}
			else if (LedCfg == CFG_LED_LINK_MUX_P60) {
				/* LED pin 60 used differently */
				pAC->GIni.GILedBlinkCtrl |= SK_LED_LINK_MUX_P60;
			}
			else if (LedCfg == CFG_LED_ACT_OFF_NOTR) {
				/* Activity LED off if no traffic */
				pAC->GIni.GILedBlinkCtrl |= SK_ACT_LED_NOTR_OFF;
			}
			else if (LedCfg == CFG_LED_COMB_ACT_LNK) {
				/* Combined Activity/Link LED mode */
				pAC->GIni.GILedBlinkCtrl |= SK_LED_COMB_ACT_LNK;
			}
		}
#ifndef SK_SLIM
		/* save HW Resources / Application Information */
		pAC->GIni.GIHwResInfo = Byte;
#endif
		if ((Byte & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {

			SK_IN8(IoC, B2_Y2_CLK_GATE, &Byte);

			if (!(Byte & Y2_STATUS_LNK2_INAC)) {
				/* Link 2 activ */
				pAC->GIni.GIMacsFound++;
			}
		}

#ifdef VCPU
		if (ChipId == CHIP_ID_YUKON_XL) {
			/* temporary WA for reported number of links */
			pAC->GIni.GIMacsFound = 2;
		}
#endif /* VCPU */

		pAC->GIni.GIChipCap = MacCfg & 0x0f;
	}
#ifndef DISABLE_YUKON_I
	else {
		pAC->GIni.GIYukon2 = SK_FALSE;
		pAC->GIni.GIValIrqMask = IS_ALL_MSK;
		pAC->GIni.GIValHwIrqMask = 0;	/* not activated */