skgeinit.c

这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码

				XsCsr = XaCsr;
			}

			if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) {
				/*
				 * Timeout of 1/18 second reached.
				 * This needs to be checked at 1/18 sec only.
				 */
				ToutCnt++;
				if (ToutCnt > 1) {
					/*
					 * If BMU stop doesn't terminate, we assume that
					 * we have a stable state and can reset the BMU,
					 * the Prefetch Unit, and RAM buffer now.
					 */
					break;			/* ===> leave do/while loop here */
				}
				/*
				 * Cache incoherency workaround: assume a start command
				 * has been lost while sending the frame.
				 */
				ToutStart = SkOsGetTime(pAC);

				if ((XsCsr & CsrStop) != 0) {
					SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStart);
				}

				if ((XaCsr & CsrStop) != 0) {
					SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStart);
				}

				/*
				 * After the previous operations the X(s|a)Csr does no
				 * longer contain the proper values
				 */
				XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);

				if (HW_SYNC_TX_SUPPORTED(pAC)) {
					XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
				}
				else {
					XsCsr = XaCsr;
				}
			}
		} while (((XsCsr & CsrTest) != CsrIdle ||
				  (XaCsr & CsrTest) != CsrIdle));

		if (pAC->GIni.GIAsfEnabled) {

			pPrt->PState = (RstMode == SK_SOFT_RST) ? SK_PRT_STOP :
				SK_PRT_RESET;
		}
		else {
			/* Reset the MAC depending on the RstMode */
			if (RstMode == SK_SOFT_RST) {

				SkMacSoftRst(pAC, IoC, Port);
			}
			else {
#ifdef SK_DIAG
				if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_1 &&
					pAC->GIni.GP[MAC_2].PState == SK_PRT_RUN) {

					pAC->GIni.GP[MAC_1].PState = SK_PRT_RESET;

					/* set GPHY Control reset */
					SK_OUT8(IoC, MR_ADDR(MAC_1, GPHY_CTRL), (SK_U8)GPC_RST_SET);
				}
				else {

					SkMacHardRst(pAC, IoC, Port);
				}
#else /* !SK_DIAG */
				SkMacHardRst(pAC, IoC, Port);
#endif /* !SK_DIAG */
			}
		}

		/* disable Force Sync bit and Enable Alloc bit */
		SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
			TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

		/* Stop Interval Timer and Limit Counter of Tx Arbiter */
		SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
		SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);

		/* Perform a local reset of the port's Tx path */
		if (CHIP_ID_YUKON_2(pAC)) {
			/* Reset the PCI FIFO of the async Tx queue */
			SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR),
				BMU_RST_SET | BMU_FIFO_RST);

			/* Reset the PCI FIFO of the sync Tx queue */
			SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR),
				BMU_RST_SET | BMU_FIFO_RST);

			/* Reset the Tx prefetch units */
			SK_OUT8(IoC, Y2_PREF_Q_ADDR(pPrt->PXaQOff, PREF_UNIT_CTRL_REG),
				PREF_UNIT_RST_SET);
			SK_OUT8(IoC, Y2_PREF_Q_ADDR(pPrt->PXsQOff, PREF_UNIT_CTRL_REG),
				PREF_UNIT_RST_SET);
		}
#ifndef DISABLE_YUKON_I
		else {
			/* Reset the PCI FIFO of the async Tx queue */
			SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
			/* Reset the PCI FIFO of the sync Tx queue */
			SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
		}
#endif /* !DISABLE_YUKON_I */
		/* Reset the RAM Buffer async Tx queue */
		SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
		/* Reset the RAM Buffer sync Tx queue */
		SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);

		/* do the reset only if ASF is not enabled */
		if (!pAC->GIni.GIAsfEnabled) {
			/* Reset Tx MAC FIFO */
			SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
		}

		/* set Pause Off */
		SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_PAUSE_OFF);
	}

	if ((Dir & SK_STOP_RX) != 0) {

		if (CHIP_ID_YUKON_2(pAC)) {
			/*
			 * The RX Stop command will not work for Yukon-2 if the BMU does not
			 * reach the end of packet and since we can't make sure that we have
			 * incoming data, we must reset the BMU while it is not during a DMA
			 * transfer. Since it is possible that the RX path is still active,
			 * the RX RAM buffer will be stopped first, so any possible incoming
			 * data will not trigger a DMA. After the RAM buffer is stopped, the
			 * BMU is polled until any DMA in progress is ended and only then it
			 * will be reset.
			 */

			/* disable the RAM Buffer receive queue */
			SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_DIS_OP_MD);

			i = 0xffff;
			while (--i) {
				SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RSL), &FifoRdShLev);
				SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RL), &FifoRdLev);

				if (FifoRdShLev == FifoRdLev) {
					break;
				}
			}

			/*
			 * If the Rx side is blocked, the above loop cannot terminate.
			 * But, if there was any traffic it should be terminated, now.
			 * However, stop the Rx BMU and the Prefetch Unit !
			 */
			SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR),
				BMU_RST_SET | BMU_FIFO_RST);
			/* reset the Rx prefetch unit */
			SK_OUT8(IoC, Y2_PREF_Q_ADDR(pPrt->PRxQOff, PREF_UNIT_CTRL_REG),
				PREF_UNIT_RST_SET);
		}
#ifndef DISABLE_YUKON_I
		else {
			/*
			 * The RX Stop Command will not terminate if no buffers
			 * are queued in the RxD ring. But it will always reach
			 * the Idle state. Therefore we can use this feature to
			 * stop the transfer of received packets.
			 */
			/* stop the port's receive queue */
			SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CsrStop);

			i = 100;
			do {
				RxCsr = TestStopBit(pAC, IoC, pPrt->PRxQOff);

				/* timeout if i==0 (bug fix for #10748) */
				if (--i == 0) {
					SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
						SKERR_HWI_E024MSG);
					break;
				}
			} while ((RxCsr & CsrTest) != CsrIdle);
			/* The path data transfer activity is fully stopped now */

			/* Perform a local reset of the port's Rx path */
			/* Reset the PCI FIFO of the Rx queue */
			SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
		}
#endif /* !DISABLE_YUKON_I */

		/* Reset the RAM Buffer receive queue */
		SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);

		/* Reset Rx MAC FIFO */
		if (!pAC->GIni.GIAsfEnabled) {
			/* Reset Rx MAC FIFO */
			SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
		}

#ifndef NDIS_MINIPORT_DRIVER	/* temp. ifndef, remove after PM module rework*/
#ifndef DISABLE_YUKON_I
		/* WA for Dev. #4.169 */
		if ((pAC->GIni.GIChipId == CHIP_ID_YUKON ||
			 pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) &&
			RstMode == SK_HARD_RST) {
			/* set Link Control reset */
			SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);

			/* clear Link Control reset */
			SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
		}
#endif /* !DISABLE_YUKON_I */
#endif /* !NDIS_MINIPORT */
	}
}	/* SkGeStopPort */


/******************************************************************************
 *
 *	SkGeInit0() - Level 0 Initialization
 *
 * Description:
 *	- Initialize the BMU address offsets
 *
 * Returns:
 *	nothing
 */
static void SkGeInit0(
SK_AC	*pAC,		/* Adapter Context */
SK_IOC	IoC)		/* I/O Context */
{
	int i;
	SK_GEPORT *pPrt;

	for (i = 0; i < SK_MAX_MACS; i++) {
		pPrt = &pAC->GIni.GP[i];

		pPrt->PState = SK_PRT_RESET;
		pPrt->PPortUsage = SK_RED_LINK;
		pPrt->PRxQOff = QOffTab[i].RxQOff;
		pPrt->PXsQOff = QOffTab[i].XsQOff;
		pPrt->PXaQOff = QOffTab[i].XaQOff;
		pPrt->PCheckPar = SK_FALSE;
#ifndef SK_SLIM
		pPrt->PIsave = 0;
		pPrt->PPrevShorts = 0;
		pPrt->PLinkResCt = 0;
		pPrt->PAutoNegTOCt = 0;
		pPrt->PPrevRx = 0;
		pPrt->PPrevFcs = 0;
		pPrt->PRxLim = SK_DEF_RX_WA_LIM;
#endif
		pPrt->PLinkMode = (SK_U8)SK_LMODE_AUTOFULL;
		pPrt->PLinkSpeedCap = (SK_U8)SK_LSPEED_CAP_1000MBPS;
		pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_1000MBPS;
		pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_UNKNOWN;
		pPrt->PLinkModeConf = (SK_U8)SK_LMODE_AUTOSENSE;
		pPrt->PFlowCtrlMode = (SK_U8)SK_FLOW_MODE_SYM_OR_REM;
#ifndef SK_SLIM
		pPrt->PLinkCap = (SK_U8)(SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL |
			SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL);
		pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
		pPrt->PFlowCtrlCap = (SK_U8)SK_FLOW_MODE_SYM_OR_REM;
		pPrt->PMSCap = 0;
		pPrt->PLipaAbil = 0;
#endif
		pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
		pPrt->PMSMode = (SK_U8)SK_MS_MODE_AUTO;
		pPrt->PMSStatus = (SK_U8)SK_MS_STAT_UNSET;
		pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
		pPrt->PEnDetMode = SK_FALSE;
		pPrt->PAutoNegFail = SK_FALSE;
		pPrt->PHWLinkUp = SK_FALSE;
		pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
#ifndef SK_SLIM
		pPrt->PLinkBroken = SK_TRUE;	/* See WA code */
		pPrt->PMacColThres = TX_COL_DEF;
		pPrt->PMacBackOffLim = TX_BOF_LIM_DEF;
		pPrt->PMacJamIpgData = TX_IPG_JAM_DEF;
		pPrt->PMacJamIpgVal = TX_JAM_IPG_DEF;
		pPrt->PMacJamLen = TX_JAM_LEN_DEF;
		pPrt->PMacDataBlind = DATA_BLIND_DEF;
		pPrt->PMacIpgData = IPG_DATA_DEF;
		pPrt->PMacLimit4 = SK_FALSE;
#endif
	}

	pAC->GIni.GILedBlinkCtrl = (SK_U16)OemConfig.Value;
	pAC->GIni.GIChipCap = 0;
	pAC->GIni.GIPexCapOffs = 0;
	pAC->GIni.GIExtLeFormat = SK_FALSE;
	pAC->GIni.GIVMainAvail = SK_TRUE;
#ifndef SK_SLIM
	pAC->GIni.GIJumTcpSegSup = SK_FALSE;
	pAC->GIni.GIGotoD3Cold = SK_FALSE;
	pAC->GIni.GITxIdxRepThres = 10;
	pAC->GIni.GINumOfRssKeys = 0;
#endif
	for (i = 0; i < 4; i++) {
		pAC->GIni.HwF.Features[i] = 0x00000000;
		pAC->GIni.HwF.OnMask[i]   = 0x00000000;
		pAC->GIni.HwF.OffMask[i]  = 0x00000000;
	}

}	/* SkGeInit0*/

#ifdef SK_PCI_RESET
/******************************************************************************
 *
 *	SkGePciReset() - Reset PCI interface
 *
 * Description:
 *	o Read PCI configuration.
 *	o Change power state to 3.
 *	o Change power state to 0.
 *	o Restore PCI configuration.
 *
 * Returns:
 *	0:	Success.
 *	1:	Power state could not be changed to 3.
 */
static int SkGePciReset(
SK_AC	*pAC,		/* Adapter Context */
SK_IOC	IoC)		/* I/O Context */
{
	int		i;
	SK_U16	PmCtlSts;
	SK_U32	Bp1;
	SK_U32	Bp2;
	SK_U16	PciCmd;
	SK_U8	Cls;
	SK_U8	Lat;
	SK_U8	ConfigSpace[PCI_CFG_SIZE];

	/*
	 * Note: Switching to D3 state is like a software reset.
	 *		 Switching from D3 to D0 is a hardware reset.
	 *		 We have to save and restore the configuration space.
	 */
	for (i = 0; i < PCI_CFG_SIZE; i++) {
		SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
	}

	/* We know the RAM Interface Arbiter is enabled. */
	SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);

	SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);

	if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
		return(1);
	}

	/* Return to D0 state. */
	SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);

	/* Check for D0 state. */
	SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);

	if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
		return(1);
	}

	/* Check PCI Config Registers. */
	SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
	SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
	SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);

	/*
	 * Compute the location in PCI config space of BAR2
	 * relativ to the location of BAR1
	 */
	if ((Bp1 & PCI_MEM_TYP_MSK) == PCI_MEM64BIT) {
		/* BAR1 is 64 bits wide */
		i = 8;
	}
	else {
		i = 4;
	}

	SkPciReadCfgDWord(pAC, PCI_BASE_1ST + i, &Bp2);
	SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);

	if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
		Lat != 0) {
		return(1);
	}

	/* Restore PCI Config Space. */
	for (i = 0; i < PCI_CFG_SIZE; i++) {
		SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
	}

	return(0);
}	/* SkGePciReset */
#endif /* SK_PCI_RESET */


/******************************************************************************
 *
 *	SkGeSetUpSupFeatures() - Collect Feature List for HW_FEATURE Macro
 *
 * Description:
 *	This function collects the available features and required
 *	deviation services of the Adapter and provides these
 *	information in the GIHwF struct. This information is used as
 *	default value and may be overritten by the driver using the
 *	SET_HW_FEATURE_MASK() macro in its Init0 phase.
 *
 * Notice:
 *	Using the On and Off mask: Never switch on the same bit in both
 *	masks simultaneously. However, if doing the Off mask will win.
 *
 * Returns:
 *	nothing
 */
static void SkGeSetUpSupFeatures(
SK_AC	*pAC,		/* Adapter Context */
SK_IOC	IoC)		/* I/O Context */
{
	int i;
	SK_U16 Word;

	switch (pAC->GIni.GIChipId) {
	case CHIP_ID_YUKON_EC:
#ifndef SK_SLIM
		pAC->GIni.GIJumTcpSegSup = SK_TRUE;
		pAC->GIni.GINumOfRssKeys = 4;
#endif
		if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_A1) {
			/* A0/A1 */
			pAC->GIni.HwF.Features[HW_DEV_LIST] =
				HWF_WA_DEV_42   | HWF_WA_DEV_46   | HWF_WA_DEV_43_418 |
				HWF_WA_DEV_420  | HWF_WA_DEV_423  | HWF_WA_DEV_424 |
				HWF_WA_DEV_425  | HWF_WA_DEV_427  | HWF_WA_DEV_428 |
				HWF_WA_DEV_483  | HWF_WA_DEV_4109 |
				HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
		}
		else {
			/* A2/A3 */
			pAC->GIni.HwF.Features[HW_DEV_LIST] =
				HWF_WA_DEV_424  | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
				HWF_WA_DEV_428  | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
				HWF_WA_DEV_4152 | HWF_WA_DEV_4167;
		}
		pAC->GIni.HwF.Features[HW_DEV_LIST] |= HWF_WA_DEV_4222 | HWF_WA_DEV_463;
		pAC->GIni.HwF.Features[HW_DEV_LIST_2] |= HWF_WA_DEV_4216;
		break;
	case CHIP_ID_YUKON_FE:
#ifndef SK_SLIM
		pAC->GIni.GINumOfRssKeys = 4;
#endif
		pAC->GIni.HwF.Features[HW_DEV_LIST] =
			HWF_WA_DEV_427  | HWF_WA_DEV_4109 | HWF_WA_DEV_463 |
			HWF_WA_DEV_4152 | HWF_WA_DEV_4167 | HWF_WA_DEV_4222;
		pAC->GIni.HwF.Features[HW_DEV_LIST_2] |= HWF_WA_DEV_4216;
		break;
	case CHIP_ID_YUKON_XL:
#ifndef SK_SLIM
		pAC->GIni.GINumOfRssKeys = 4;
		pAC->GIni.GIJumTcpSegSup = SK_TRUE;
#endif