📄 skgeinit.h

📁 这是Marvell Technology Group Ltd. 4355 (rev 12)网卡在linux下的驱动程序源代码
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#define HWF_TX_TCP_CSUM_SUP		0x20100000UL	/* TCP Tx checksum supported */#define HWF_TX_UDP_CSUM_SUP		0x20080000UL	/* UDP Tx checksum supported */#define HWF_RX_CSUM_SUP			0x20040000UL	/* RX checksum supported */#define HWF_TCP_SEGM_SUP		0x20020000UL	/* TCP segmentation supported */#define HWF_RSS_HASH_SUP		0x20010000UL	/* RSS Hash supported */#define HWF_PORT_VLAN_SUP		0x20008000UL	/* VLAN can be config per port*/#define HWF_ROLE_PARAM_SUP		0x20004000UL	/* Role parameter supported */#define HWF_LOW_PMODE_SUP		0x20002000UL	/* Low Power Mode supported */#define HWF_ENERGIE_DEMO_SUP	0x20001000UL	/* Energy Detect mode supp. */#define HWF_SPEED1000_SUP		0x20000800UL	/* Line Speed 1000 supported */#define HWF_SPEED100_SUP		0x20000400UL	/* Line Speed 100 supported */#define HWF_SPEED10_SUP			0x20000200UL	/* Line Speed 10 supported */#define HWF_AUTONEGSENSE_SUP	0x20000100UL	/* Autoneg Sense supported */#define HWF_PHY_LOOPB_MD_SUP	0x20000080UL	/* PHY loopback mode supp. */#define HWF_ASF_SUP				0x20000040UL	/* ASF support possible */#define HWF_QS_STEPS_1KB		0x20000020UL	/* The Rx/Tx queues can be */												/* configured with 1 kB res. */#define HWF_OWN_RAM_PER_PORT	0x20000010UL	/* Each port has a separate */												/* RAM buffer */#define HWF_MIN_LED_IF			0x20000008UL	/* Minimal LED interface */												/* (e.g. for Yukon-EC) */#define HWF_LIST_ELEMENTS_USED	0x20000004UL	/* HW uses list elements */												/* (otherwise desc. are used) */#define HWF_GMAC_INSIDE			0x20000002UL	/* Device contains GMAC */#define HWF_TWSI_PRESENT		0x20000001UL	/* TWSI sensor bus present */#endif/* DWORD 3: still unused *//* * HW_FEATURE()	-	returns whether the feature is serviced or not */#define HW_FEATURE(pAC, ReqFeature) \	(((pAC)->GIni.HwF.Features[((ReqFeature) & 0x30000000UL) >> 28] &\	 ((ReqFeature) & 0x0fffffffUL)) != 0)#define HW_FEAT_LIST	0#define HW_DEV_LIST		1#define HW_DEV_LIST_2	2#define SET_HW_FEATURE_MASK(pAC, List, OffMaskValue, OnMaskValue) {	\	if ((List) == HW_FEAT_LIST || (List) == HW_DEV_LIST) {			\		(pAC)->GIni.HwF.OffMask[List] = (OffMaskValue);				\		(pAC)->GIni.HwF.OnMask[List] = (OnMaskValue);				\	}																\}/* driver access macros for GIni structure ***********************************/#define CHIP_ID_YUKON_2(pAC)		((pAC)->GIni.GIYukon2)#define HW_SYNC_TX_SUPPORTED(pAC)					\	((pAC)->GIni.GIChipId == CHIP_ID_YUKON		||	\	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_LITE	||	\	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_XL)#define HW_HAS_NEWER_PHY(pAC)						\	((pAC)->GIni.GIChipId == CHIP_ID_YUKON_XL	||	\	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_EC_U	||	\	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_EX	||	\	 (pAC)->GIni.GIChipId >= CHIP_ID_YUKON_SUPR)#define HW_MS_TO_TICKS(pAC, MsTime) \	((MsTime) * (62500L/100) * (pAC)->GIni.GIHstClkFact)#define HW_IS_EXT_LE_FORMAT(pAC)	((pAC)->GIni.GIExtLeFormat)#define HW_IS_NEW_ASF_FORMAT(pAC)	((pAC)->GIni.GIExtLeFormat)/* Is RAM buffer available? */#define HW_IS_RAM_IF_AVAIL(pAC)						\	((pAC)->GIni.GIChipId == CHIP_ID_YUKON		||	\	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_LITE	||	\	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_XL	||	\	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_EC	||	\	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_FE)#define HW_NUM_OF_PATTERN(pAC)	((pAC)->GIni.GINumOfPattern)#define HW_OTP_SUPPORTED(pAC)	((pAC)->GIni.GIChipId == CHIP_ID_YUKON_FE_P || \								 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_UL_2)/* general CSUM *//* flag to distinguish between old style and new style csum offload */#define HW_SUP_FULL_OFFLOAD(pAC)		((pAC)->GIni.GIExtLeFormat)#define HW_SUP_NEW_LSOV1(pAC)			((pAC)->GIni.GIExtLeFormat)/* Rx CSUM IPv4 */#define HW_SUP_RX_CSUM_IPV4(pAC)		SK_TRUE#define HW_SUP_RX_CSUM_OPT_IPV4(pAC)	((pAC)->GIni.GIExtLeFormat)#define HW_SUP_RX_CSUM_TCPIPV4(pAC)		SK_TRUE#define HW_SUP_RX_CSUM_OPT_TCPIPV4(pAC)	((pAC)->GIni.GIExtLeFormat)#define HW_SUP_RX_CSUM_UDPIPV4(pAC)		SK_TRUE/* Rx CSUM IPv6 */#define HW_SUP_RX_CSUM_IPV6_EXT_HDR(pAC)((pAC)->GIni.GIExtLeFormat)#define HW_SUP_RX_CSUM_TCPIPV6(pAC)		((pAC)->GIni.GIExtLeFormat)#define HW_SUP_RX_CSUM_OPT_TCPIPV6(pAC)	((pAC)->GIni.GIExtLeFormat)#define HW_SUP_RX_CSUM_UDPIPV6(pAC)		((pAC)->GIni.GIExtLeFormat)/* Tx CSUM IPv4 */#define HW_SUP_TX_CSUM_IPV4(pAC)		((pAC)->GIni.GIExtLeFormat)#define HW_SUP_TX_CSUM_OPT_IPV4(pAC)	((pAC)->GIni.GIExtLeFormat)#define HW_SUP_TX_CSUM_TCPIPV4(pAC)		(!HW_FEATURE(pAC, HWF_WA_DEV_4185CS))#define HW_SUP_TX_CSUM_OPT_TCPIPV4(pAC)	((pAC)->GIni.GIExtLeFormat)#define HW_SUP_TX_CSUM_UDPIPV4(pAC)		(!HW_FEATURE(pAC, HWF_WA_DEV_4185CS))/* Tx CSUM IPv6 */#define HW_SUP_TX_CSUM_IPV6_EXT_HDR(pAC)((pAC)->GIni.GIExtLeFormat)#define HW_SUP_TX_CSUM_TCPIPV6(pAC)		((pAC)->GIni.GIExtLeFormat)#define HW_SUP_TX_CSUM_OPT_TCPIPV6(pAC)	((pAC)->GIni.GIExtLeFormat)#define HW_SUP_TX_CSUM_UDPIPV6(pAC)		((pAC)->GIni.GIExtLeFormat)/* Tx CSUM special flag for FiFo size */#define HW_SUP_TX_CSUM_FOR_JUMBO(pAC)	(		\	(pAC)->GIni.GIJumTcpSegSup ||				\	(pAC)->GIni.GIChipId == CHIP_ID_YUKON ||	\	(pAC)->GIni.GIChipId == CHIP_ID_YUKON_LITE)/* LSO */#define HW_SUP_LSOV1(pAC)				((pAC)->GIni.GIYukon2)#define HW_SUP_OPT_IPV4_LSOV1(pAC)		((pAC)->GIni.GIYukon2)#define HW_SUP_OPT_TCPIPV4_LSOV1(pAC)	((pAC)->GIni.GIYukon2)#define HW_SUP_LSOV2(pAC)				((pAC)->GIni.GIExtLeFormat)#define HW_SUP_IPV6_EXT_HDR_LSOV2(pAC)	((pAC)->GIni.GIExtLeFormat)#define HW_SUP_OPT_TCPIPV6_LSOV2(pAC)	((pAC)->GIni.GIExtLeFormat)#define HW_SUP_LSO_FOR_JUMBO(pAC)		((pAC)->GIni.GIJumTcpSegSup)/* RSS */#define HW_SUP_IPV4_RSS(pAC)			((pAC)->GIni.GIYukon2 &&			\										  !HW_FEATURE(pAC, HWF_WA_DEV_4152))/*  * IPV6_RSS is supported since Yukon-Extreme B0 * To avoid that IPV6 RSS is executed on Extreme A0 (which is opsolete already) * the HW_SUM_IPV6_RSS condition needs to be combined with the term  * "&& !HW_FEATURE(pAC, HWF_WA_DEV_LIM_IPV6_RSS)" */#define HW_SUP_IPV6_RSS(pAC)			((pAC)->GIni.GIExtLeFormat)/* MACSec */#define HW_SUP_MACSEC(pAC)							\	((pAC)->GIni.GIChipId == CHIP_ID_YUKON_EX ||	\	 (pAC)->GIni.GIChipId == CHIP_ID_YUKON_SUPR)/* VPD Support */#define HW_SUP_VPD(pAC)			((pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE_P)/* SPI PROM Support */#define HW_SUP_SPI_PROM(pAC)	((pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE_P &&	\								 (pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE)/* Battery Power Management */#define HW_NO_BAT_POW_MANAGEMENT(pAC)				\	((pAC)->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&	\	 (pAC)->GIni.GIChipRev > CHIP_REV_YU_EC_U_A0 &&	\	 (pAC)->GIni.GIChipCap == 2 &&					\	 !HW_FEATURE(pAC, HWF_WA_DEV_4200))/* maximal supported link speed; returns 100 or 1000 */#define HW_MAX_LINE_SPEED(pAC)							\	((pAC)->GIni.GP[MAC_1].PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS ? 1000 : 100)/* Hardware has free usable Timestamp Timer */#define HW_SUP_FREE_TS_TIMER(pAC)						\	((pAC)->GIni.GIChipId >= CHIP_ID_YUKON_FE_P ||		\	((pAC)->GIni.GIChipId == CHIP_ID_YUKON_EX &&		\	((pAC)->GIni.GIChipCap & CHIP_CAP_MSK_EX_B1) == 0))/* structures *****************************************************************//* * HW Feature structure */typedef struct s_HwFeatures {	SK_U32	Features[4];	/* Feature list */	SK_U32	OffMask[4];		/* Off Mask */	SK_U32	OnMask[4];		/* On Mask */} SK_HW_FEATURES;/* * MAC specific functions */typedef struct s_GeMacFunc {	int	(*pFnMacUpdateStats)(SK_AC *, SK_IOC, unsigned int);	int	(*pFnMacStatistic)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U32 SK_FAR *);	int	(*pFnMacResetCounter)(SK_AC *, SK_IOC, unsigned int);	int	(*pFnMacOverflow)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U64 SK_FAR *);	void (*pSkGeSirqIsr)(SK_AC *, SK_IOC, SK_U32);#ifdef SK_DIAG	int	(*pFnMacPhyRead)(SK_AC *, SK_IOC, int, int, SK_U16 SK_FAR *);	int	(*pFnMacPhyWrite)(SK_AC *, SK_IOC, int, int, SK_U16);#endif /* SK_DIAG */} SK_GEMACFUNC;/* * Port Structure */typedef	struct s_GePort {#ifndef SK_DIAG	SK_TIMER	PWaTimer;	/* Workaround Timer */	SK_TIMER	HalfDupChkTimer;	SK_TIMER	PPauseTimer;/* Pause Packet Timer */	SK_U32		PPauseTxCnt;/* Pause Packet Counter (Tx) */	SK_BOOL		PPauseFlag;	/* Pause Packet Flag */#endif /* !SK_DIAG */#ifndef SK_SLIM	SK_U32	PPrevShorts;	/* Previous Short Counter checking */	SK_U32	PPrevFcs;		/* Previous FCS Error Counter checking */	SK_U64	PPrevRx;		/* Previous RxOk Counter checking */	SK_U64	PRxLim;			/* Previous RxOk Counter checking */	SK_U64	LastOctets;		/* For half duplex hang check */	int		PLinkResCt;		/* Link Restart Counter */	int		PAutoNegTimeOut;/* Auto-negotiation timeout current value */	int		PAutoNegTOCt;	/* Auto-negotiation Timeout Counter */#endif	int		PRxQSize;		/* Port Rx Queue Size in kB */	int		PXSQSize;		/* Port Synchronous  Transmit Queue Size in kB */	int		PXAQSize;		/* Port Asynchronous Transmit Queue Size in kB */	SK_U32	PRxQRamStart;	/* Receive Queue RAM Buffer Start Address */	SK_U32	PRxQRamEnd;		/* Receive Queue RAM Buffer End Address */	SK_U32	PXsQRamStart;	/* Sync Tx Queue RAM Buffer Start Address */	SK_U32	PXsQRamEnd;		/* Sync Tx Queue RAM Buffer End Address */	SK_U32	PXaQRamStart;	/* Async Tx Queue RAM Buffer Start Address */	SK_U32	PXaQRamEnd;		/* Async Tx Queue RAM Buffer End Address */#ifndef SK_SLIM	SK_U32	PRxOverCnt;		/* Receive Overflow Counter */#endif	int		PRxQOff;		/* Rx Queue Address Offset */	int		PXsQOff;		/* Synchronous Tx Queue Address Offset */	int		PXaQOff;		/* Asynchronous Tx Queue Address Offset */	int		PhyType;		/* PHY used on this port */	int		PState;			/* Port status (reset, stop, init, run) */	int		PPortUsage;		/* Driver Port Usage */	SK_U16	PhyId1;			/* PHY Id1 on this port */	SK_U16	PhyAddr;		/* MDIO/MDC PHY address */	SK_U16	PGmANegAdv;		/* Saved GPhy AutoNegAdvertisment register */	SK_BOOL	PHWLinkUp;		/* The hardware Link is up (wiring) */	SK_BOOL	PCheckPar;		/* Do we check for parity errors ? */#ifndef SK_SLIM	SK_U16	PSsave;			/* Saved PHY status word */	SK_U16	PIsave;			/* Saved Interrupt status word */	SK_BOOL	PLinkBroken;	/* Is Link broken ? */	SK_BOOL	HalfDupTimerActive;#endif	SK_U8	PLinkModeConf;	/* Link Mode configured */	SK_U8	PLinkMode;		/* Link Mode currently used */	SK_U8	PLinkModeStatus;/* Link Mode Status */	SK_U8	PLinkSpeedCap;	/* Link Speed Capabilities (10/100/1000 Mbps) */	SK_U8	PLinkSpeed;		/* configured Link Speed (10/100/1000 Mbps) */	SK_U8	PLinkSpeedUsed;	/* current Link Speed (10/100/1000 Mbps) */	SK_U8	PFlowCtrlMode;	/* Flow Control Mode */	SK_U8	PFlowCtrlStatus;/* Flow Control Status */#ifndef SK_SLIM	SK_U8	PLinkCap;		/* Link Capabilities */	SK_U8	PFlowCtrlCap;	/* Flow Control Capabilities */	SK_U8	PMSCap;			/* Master/Slave Capabilities */	SK_U16	PLipaAbil;		/* Link Partner Ability */#endif	SK_U8	PMSMode;		/* Master/Slave Mode */	SK_U8	PMSStatus;		/* Master/Slave Status */	SK_BOOL	PEnDetMode;		/* Energy Detect Mode */	SK_BOOL	PAutoNegFail;	/* Auto-negotiation fail flag */	SK_U8	PLipaAutoNeg;	/* Auto-negotiation possible with Link Partner */	SK_U8	PPhyPowerState;	/* PHY current power state */	SK_U16	PMacAddr[3];	/* MAC address */#ifndef SK_SLIM	SK_U8	PCableLen;		/* Cable Length */	SK_U8	PMdiPairLen[4];	/* MDI[0..3] Pair Length */	SK_U8	PMdiPairSts[4];	/* MDI[0..3] Pair Diagnostic Status */	int		PMacColThres;	/* MAC Collision Threshold */	int		PMacBackOffLim;	/* MAC Back-off Limit */	int		PMacJamIpgData;	/* MAC IPG Jam to Data */	int		PMacJamIpgVal;	/* MAC Jam IPG */	int		PMacJamLen;		/* MAC Jam length */	int		PMacDataBlind;	/* MAC Data Blinder */	int		PMacIpgData;	/* MAC Data IPG */	SK_BOOL PMacLimit4;		/* reset collision counter and backoff algorithm */#endif} SK_GEPORT;/* * Gigabit Ethernet Initialization Struct * (has to be included in the adapter context) */typedef	struct s_GeInit {	int			GIChipId;		/* Chip Identification Number */	int			GIChipRev;		/* Chip Revision Number */	SK_U8		GIPciHwRev;		/* PCI HW Revision Number */	SK_U8		GIPciBus;		/* PCI Bus Type (PCI / PCI-X / PCI-Express) */	SK_U8		GIPciMode;		/* PCI / PCI-X Mode @ Clock */	SK_U8		GIPexWidth;		/* PCI-Express Negotiated Link Width */	SK_BOOL		GIYukonLite;	/* YUKON-Lite chip */	SK_BOOL		GIYukon2;		/* YUKON-2 chip (-XL, -EC or -FE) */	SK_U8		GIConTyp;		/* Connector Type */	SK_U8		GIPmdTyp;		/* PMD Type */	SK_BOOL		GICopperType;	/* Copper Type adapter ? */	SK_BOOL		GIPciSlot64;	/* 64-bit PCI Slot */	SK_BOOL		GIPciClock66;	/* 66 MHz PCI Clock */	SK_BOOL		GIVauxAvail;	/* VAUX available (YUKON) */	SK_BOOL		GIVMainAvail;	/* VMAIN available */	SK_BOOL		GIYukon32Bit;	/* 32-Bit YUKON adapter */	SK_BOOL		GIAsfEnabled;	/* ASF subsystem enabled */	SK_BOOL		GIAsfRunning;	/* ASF subsystem running */	SK_BOOL		GIExtLeFormat;	/* Extended list element format (Yukon-Ext) */#ifndef SK_SLIM	SK_BOOL		GIJumTcpSegSup;	/* TCP Segmentation of Jumbo frames supported ?*/	SK_BOOL		GIGotoD3Cold;	/* System set to D3cold */#endif	SK_U16		GILedBlinkCtrl;	/* LED Blink Control */	int			GIMacsFound;	/* Number of MACs found on this adapter */	int			GIMacType;		/* MAC Type used on this adapter */	int			GIChipCap;		/* Adapter's Capabilities */#ifndef SK_SLIM	int			GIHwResInfo;	/* HW Resources / Application Information */#endif	int			GIHstClkFact;	/* Host Clock Factor (HstClk / 62.5 * 100) */	int			GILevel;		/* Initialization Level completed */	int			GIRamSize;		/* The RAM size of the adapter in kB */	int			GIPexCapOffs;	/* PCI-E Capability Reg Off (moved in Y-Ex B0)*/#ifndef SK_SLIM	int			GIWolOffs;		/* WOL Register Offset (HW-Bug in Rev. A) */	int			GINumOfPattern;	/* Number of Pattern supported by HW */	int			GINumOfRssKeys;	/* Number of supported RSS keys */	int			GITxIdxRepThres;/* Tx Index reporting threshold */#endif	SK_U32		GIRamOffs;		/* RAM Address Offset for addr calculation */	SK_U32		GIPollTimerVal;	/* Descr. Poll Timer Init Val (HstClk ticks) */	SK_U32		GIValIrqMask;	/* Value for Interrupt Mask */	SK_U32		GIValHwIrqMask;	/* Value for HWE Interrupt Mask */#ifndef SK_SLIM	SK_U32		GITimeStampCnt;	/* Time Stamp High Counter (YUKON only) */#endif	SK_GEPORT	GP[SK_MAX_MACS];/* Port Dependent Information */	SK_HW_FEATURES HwF;			/* HW Features struct */	SK_GEMACFUNC GIFunc;		/* MAC depedent functions */} SK_GEINIT;/* * Error numbers and messages for skxmac2.c and skgeinit.c */#define SKERR_HWI_E001		(SK_ERRBASE_HWINIT+1)#define SKERR_HWI_E001MSG	"SkXmClrExactAddr() has got illegal parameters"#define SKERR_HWI_E002		(SKERR_HWI_E001+1)#define SKERR_HWI_E002MSG	"SkGeInit(): Level 1 call missing"#define SKERR_HWI_E003		(SKERR_HWI_E002+1)#define SKERR_HWI_E003MSG	"SkGeInit() called with illegal init Level"#define SKERR_HWI_E004		(SKERR_HWI_E003+1)#define SKERR_HWI_E004MSG	"SkGeInitPort(): Queue Size illegal configured"#define SKERR_HWI_E005		(SKERR_HWI_E004+1)#define SKERR_HWI_E005MSG	"SkGeInitPort(): cannot init running ports"#define SKERR_HWI_E006		(SKERR_HWI_E005+1)#define SKERR_HWI_E006MSG	"SkGeInit() called with illegal Chip Id"#define SKERR_HWI_E007		(SKERR_HWI_E006+1)#define SKERR_HWI_E007MSG	"SkXmInitDupMd() called with invalid Dup Mode"#define SKERR_HWI_E008		(SKERR_HWI_E007+1)#define SKERR_HWI_E008MSG	"SkXmSetRxCmd() called with invalid Mode"#define SKERR_HWI_E009		(SKERR_HWI_E008+1)#define SKERR_HWI_E009MSG	"SkGeCfgSync() called although PXSQSize zero"#define SKERR_HWI_E010		(SKERR_HWI_E009+1)#define SKERR_HWI_E010MSG	"SkGeCfgSync() called with invalid parameters"#define SKERR_HWI_E011		(SKERR_HWI_E010+1)#define SKERR_HWI_E011MSG	"SkGeInitPort(): Receive Queue Size too small"#define SKERR_HWI_E012		(SKERR_HWI_E011+1)#define SKERR_HWI_E012MSG	"SkGeInitPort(): invalid Queue Size specified"#define SKERR_HWI_E013		(SKERR_HWI_E012+1)#define SKERR_HWI_E013MSG	"SkGeInitPort(): cfg changed for running queue"#define SKERR_HWI_E014		(SKERR_HWI_E013+1)#define SKERR_HWI_E014MSG	"SkGeInitPort(): unknown PortUsage specified"#define SKERR_HWI_E015		(SKERR_HWI_E014+1)#define SKERR_HWI_E015MSG	"Illegal Link Mode parameter"#define SKERR_HWI_E016		(SKERR_HWI_E015+1)#define SKERR_HWI_E016MSG	"Illegal Flow Control Mode parameter"#define SKERR_HWI_E017		(SKERR_HWI_E016+1)#define SKERR_HWI_E017MSG	"Illegal value specified for GIPollTimerVal"#define SKERR_HWI_E018		(SKERR_HWI_E017+1)#define SKERR_HWI_E018MSG	"FATAL: SkGeStopPort() does not terminate (Tx)"#define SKERR_HWI_E019		(SKERR_HWI_E018+1)#define SKERR_HWI_E019MSG	"Illegal Speed parameter"#define SKERR_HWI_E020		(SKERR_HWI_E019+1)#define SKERR_HWI_E020MSG	"Illegal Master/Slave parameter"#define SKERR_HWI_E021		(SKERR_HWI_E020+1)#define SKERR_HWI_E021MSG	"MacUpdateStats(): cannot update statistic counter"#define SKERR_HWI_E022		(SKERR_HWI_E021+1)#define SKERR_HWI_E022MSG	"MacStatistic(): illegal statistic base address"#define SKERR_HWI_E023		(SKERR_HWI_E022+1)
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